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Circuit arrangement for the summation of products formed by analog signals and digital coefficients

机译:用于模拟信号和数字系数乘积求和的电路布置

摘要

A circuit arrangement is disclosed for the summation of products formed from analog signals and digital coefficients. A multiplying digital-analog converter is provided having a reference input for receiving analog signals at successive points in time. A data input of the digital-analog converter receives digital coefficients assigned to the respective analog signals. A summation stage connected to output signals of the digital-analog converter integrates over a predetermined time period the output signals of the digital-analog converter representative of products of the analog signals and digital coefficients.
机译:公开了一种用于对由模拟信号和数字系数形成的乘积求和的电路装置。提供了具有参考输入的乘法数模转换器,该参考输入用于在连续的时间点接收模拟信号。数模转换器的数据输入接收分配给各个模拟信号的数字系数。连接到数模转换器的输出信号的求和级在预定的时间段上对代表模拟信号和数字系数的乘积的数模转换器的输出信号进行积分。

著录项

  • 公开/公告号US4159524A

    专利类型

  • 公开/公告日1979-06-26

    原文格式PDF

  • 申请/专利权人 SIEMENS AG;

    申请/专利号US19770858160

  • 申请日1977-12-07

  • 分类号G06J1/00;

  • 国家 US

  • 入库时间 2022-08-22 19:17:16

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