首页> 外国专利> MEMORY ERROR LOGGER FOR DISTINGUISHING SOLID ERROR FROM TRANSIENT ERROR

MEMORY ERROR LOGGER FOR DISTINGUISHING SOLID ERROR FROM TRANSIENT ERROR

机译:内存错误记录器,用于将固态错误与瞬态错误区分开

摘要

A method of and an apparatus for distinguishing between transient and solid errors within a single-error-correcting semiconductor memory storage unit (MSU) comprised of a plurality of large scale integrated (LSI) bit planes and for notifying the associated data processing system of required maintenance action. The method utilizes an error logging store (ELS) that is comprised of a plurality of memory error registers one for each separately associated word group within the MSU. Each memory error register contains storage for: (1) the Error Correction Code (ECC) defined, failing bit position; (2) the single bit error counter; (3) the multiple single bit error tag; and (4) the multiple bit error tag. Upon detection of an error within a word group, the associated memory error register is accessed to determine the history of previously detected errors within that word group. The central processing unit (CPU) is notified by a priority interrupt of the error status of that word group if: (1) the number of consecutive errors within a word group at the same bit position reaches a set threshold indicating the high probability of a solid single bit error; or (2) the error detected is in a different bit position from that previously identified as a solid single bit error indicating the high probability of a future uncorrectable multiple-bit error. This method and apparatus notifies the CPU of the likelihood of imminent uncorrectable errors and maintains a history of the error indications that lead to that conclusion.
机译:一种用于在由多个大规模集成(LSI)位平面组成的单错误校正半导体存储器存储单元(MSU)中区分瞬时错误和实体错误并向相关数据处理系统通知所需方法和装置的方法和设备维护行动。该方法利用了错误日志存储(ELS),该错误日志存储由多个存储器错误寄存器组成,每个MSU内的每个单独关联的字组都有一个。每个存储器错误寄存器都包含以下存储:(1)定义的错误校正码(ECC),失败位的位置; (2)单位错误计数器; (3)多个单位错误标签; (4)多位错误标签。一旦检测到字组内的错误,就访问相关的存储器错误寄存器以确定该字组内先前检测到的错误的历史。如果满足以下条件,则通过优先级中断将该字组的错误状态通知给中央处理单元(CPU):(1)相同位位置上的字组内连续错误的数量达到设置的阈值,表明出现错误的可能性很高。可靠的单个位错误;或(2)所检测到的错误与先前标识为实心单个错误的错误位置不同,指示将来发生不可纠正的多位错误的可能性很高。该方法和设备将即将发生的不可纠正错误的可能性通知给CPU,并维护导致该结论的错误指示的历史记录。

著录项

  • 公开/公告号JPS5486245A

    专利类型

  • 公开/公告日1979-07-09

    原文格式PDF

  • 申请/专利权人 SPERRY RAND CORP;

    申请/专利号JP19780149584

  • 发明设计人 SUPERI YUNIBATSUKU DEIRU KENIS;

    申请日1978-12-02

  • 分类号G06F12/16;G06F11/00;G06F11/07;G06F11/10;G06F11/34;

  • 国家 JP

  • 入库时间 2022-08-22 21:01:44

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