首页> 外国专利> DATA PROCESSING SYSTEM FOR TRANSFERRING TO MICROPROGRAM CONTROLLER BY HARDWARE CONTROL AND RESETTING VIA MICROINSTRUCTION RESTARTING CODE

DATA PROCESSING SYSTEM FOR TRANSFERRING TO MICROPROGRAM CONTROLLER BY HARDWARE CONTROL AND RESETTING VIA MICROINSTRUCTION RESTARTING CODE

机译:通过硬件指令重新启动代码通过硬件控制转移到微程序控制器的数据处理系统

摘要

A microprogrammed pipeline data processing unit includes a first control store, a second control store and a plurality of hardware sequence control circuits. The first control store includes a plurality of storage locations, each location for storing an address field and a control sequence field for each program instruction required to be executed by the processing unit. The second control store includes a plurality of groups of storage locations, each group storing microinstructions required for executing at least a portion of at least one program instruction. Each sequence includes at least one microinstruction which contains a restart field coded to specify the conditions under which the hardware sequence circuits continue instruction execution. For each program instruction which can not be executed by the plurality of hardware sequence circuits in a pipeline mode, the control sequence field is coded to include a predetermined bit pattern. When decoded, the hardware sequence circuits is conditioned to enter an escape state enabling control to be transferred to a sequence specified by the address field. Instruction execution proceeds under microprogram control while the hardware sequence circuits remain in the same state. Upon the decoding of a microinstruction containing a restart field, the hardware sequence circuits are switched from the escape state to a state which enables the continuing of hardware instruction execution in a pipeline mode.
机译:微程序化管线数据处理单元包括第一控制存储器,第二控制存储器和多个硬件序列控制电路。第一控制存储器包括多个存储位置,每个位置用于存储需要由处理单元执行的每个程序指令的地址字段和控制序列字段。第二控制存储器包括多组存储位置,每组存储执行至少一个程序指令的至少一部分所需的微指令。每个序列包括至少一个微指令,该微指令包含一个重新启动字段,该重新启动字段编码为指定硬件序列电路继续执行指令的条件。对于在管线模式下不能由多个硬件序列电路执行的每个程序指令,控制序列字段被编码为包括预定的位模式。解码时,硬件序列电路将进入退出状态,以便将控制权转移到地址字段指定的序列。指令执行在微程序控制下进行,而硬件序列电路保持相同状态。在对包含重启字段的微指令进行解码时,硬件序列电路从转义状态切换到能够以流水线模式继续执行硬件指令的状态。

著录项

  • 公开/公告号JPS54109345A

    专利类型

  • 公开/公告日1979-08-27

    原文格式PDF

  • 申请/专利权人 HONEYWELL INF SYSTEMS;

    申请/专利号JP19780143494

  • 发明设计人 JIYOI II UIRUHAITO;

    申请日1978-11-22

  • 分类号G06F9/22;G06F9/26;G06F9/28;G06F9/38;

  • 国家 JP

  • 入库时间 2022-08-22 21:19:44

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