首页> 外国专利> process for the manufacture of a half geleiderinrichting with a contact part of a shallow diffusielaag.

process for the manufacture of a half geleiderinrichting with a contact part of a shallow diffusielaag.

机译:与浅扩散层接触部分接触的半凝胶富集的制备方法。

摘要

A semiconductor element is made with a diffusion layer which is deeper where it is covered by a contact; and with a layer of heat resisting metal, pref. polycrystalline Si (I) used as a conductor. A substrate of conductivity (a) is covered by a layer (II) of insulation which is selectively removed to form a window for a contact, and the device is then covered by (I). Impurities of conductivity (b) are diffused through (I) and the window to form a zone (Z1) in the substrate with thickness (t1). Layer (II) and the (I) are partly removed to leave a mask permitting further diffusion of impurities of conductivity (b) into the substrate to form a zone (Z2) adjacent to zone (Z1) and with a thickness (t2) greater than (t1). A contact is then applied to zone (Z1). Zone (Z1) is pref. obtd. by thermal diffusion and zone (Z2) by ion implantation. Method us used for mfr. of MIS-FETs, to avoid the usual disadvantages and to increase the switching speed of the devices without increasing the number of mfg. operations. The method can also be used on other semiconductors e.g. bipolar resistor or capacitive-elements.
机译:半导体元件由扩散层制成,该扩散层在被触点覆盖的位置更深。并带有一层耐热金属。多晶Si(I)用作导体。电导率(a)的基板被绝缘层(II)覆盖,该绝缘层被有选择地去除以形成用于接触的窗口,然后器件被(I)覆盖。导电性杂质(b)通过(I)和窗口扩散,从而在基板上形成厚度为(t1)的区域(Z1)。层(II)和(I)被部分去除以留下掩模,从而允许导电性(b)的杂质进一步扩散到衬底中,以形成与区域(Z1)相邻的区域(Z2),并且厚度(t2)更大比(t1)。然后将触点应用于区域(Z1)。区域(Z1)为首选项。 t。通过热扩散和区域(Z2)通过离子注入。我们用于mfr的方法。为了避免常见的缺点并提高器件的开关速度而又不增加mfg的数量,采用了MIS-FET。操作。该方法还可以用在其他半导体例如半导体上。双极电阻器或电容性元件。

著录项

  • 公开/公告号NL7706436A

    专利类型

  • 公开/公告日1977-12-20

    原文格式PDF

  • 申请/专利权人 HITACHI LIMITED TE TOKIO.;

    申请/专利号NL19770006436

  • 发明设计人

    申请日1977-06-10

  • 分类号H01L21/225;H01L21/265;H01L29/78;

  • 国家 NL

  • 入库时间 2022-08-22 22:47:13

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