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Digital filter circuit for linear differential equation characteristic - integrators in series with constant multipliers minimise scanning time
Digital filter circuit for linear differential equation characteristic - integrators in series with constant multipliers minimise scanning time
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机译:用于线性微分方程特性的数字滤波器电路-与常数乘法器串联的积分器可最大限度地减少扫描时间
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摘要
A digital filter circuit operates with a small scanning period to minimise the scanning error. The circuit utilises 'n' integrators in series operating with 'n' multipliers handling constants to generate output frequencies that are added and the subtracted from the input signal. Six integrators in series generate outputs that are multiplied with constants. The outputs of each successive multiplier stage are summed. The output of the highest order summing stage represents complete addition of all multiplier outputs, and is subtracted from the reference input to generate the error signal. The output is generated by summing the outputs of the last three integrating stages.
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