首页> 外国专利> Digital filter circuit for linear differential equation characteristic - integrators in series with constant multipliers minimise scanning time

Digital filter circuit for linear differential equation characteristic - integrators in series with constant multipliers minimise scanning time

机译:用于线性微分方程特性的数字滤波器电路-与常数乘法器串联的积分器可最大限度地减少扫描时间

摘要

A digital filter circuit operates with a small scanning period to minimise the scanning error. The circuit utilises 'n' integrators in series operating with 'n' multipliers handling constants to generate output frequencies that are added and the subtracted from the input signal. Six integrators in series generate outputs that are multiplied with constants. The outputs of each successive multiplier stage are summed. The output of the highest order summing stage represents complete addition of all multiplier outputs, and is subtracted from the reference input to generate the error signal. The output is generated by summing the outputs of the last three integrating stages.
机译:数字滤波器电路以较小的扫描周期工作,以最小化扫描误差。该电路利用与“ n”个乘法器串联处理的“ n”个积分器来处理常数,以生成输出频率,该输出频率要与输入信号相加或相减。六个串联的积分器产生的输出乘以常数。将每个连续的乘法器级的输出相加。最高阶求和级的输出代表所有乘法器输出的完全加法,并从参考输入中减去以产生误差信号。通过将最后三个积分级的输出相加来生成输出。

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