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IMPROVEMENTS IN OR RELATING TO PARITY CHECKING CIRCUITS
IMPROVEMENTS IN OR RELATING TO PARITY CHECKING CIRCUITS
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机译：平价检查电路或与平价检查电路有关的改进
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摘要
1279182 Logic circuits; parity checking; digital transmission systems SIEMENS AG 8 June 1970 [9 June 1969] 27522/70 Headings H3T and H4P A logic circuit for three input signals a, b and c comprises four common emitter transistor pairs and a transistor output circuit T11, T12 arranged substantially as shown whereby it may indicate the presence of one and three of the signals (i.e. an odd number) or with some reversal of connections the presence of none and any two only (i.e. an even number). In the circuit as shown the transistors T1 to T6 perform the logic Z=a.b+a.b and z=a.b+a.b Transistors T9 and T10 perform the logic c(a.b+a.b) and c(a.b+a.b). When these signals are combined by T11 and T12 the circuit performs the logic a.b.c+a.b.c+a.b.c+a.b.c (which is also the summing output of a full adder). Transistor 8 is a level shifter and the diodes limit the voltage drop across the associated collector resistors. The even function a.b.c+a.b.c. +a.b.c+a.b.c may be obtained by reversing the connections to T9 and T10, at collector or base, or the base connections of T5 and T6 as by altering external connections to the circuit chip. Higher orders of even or odd parity may be obtained by one of a number of the circuits (Fig. 2, not shown) either of the same or of mixed parity types. In the latter case, conversion from even to odd may be effected by altering the connections to the output logic only.
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