PARALLEL COMPUTATION ARCHITECTURE WITH RECONFIGURABLE CORE LEVEL AND VECTOR LEVEL PARALLELITY

• 1. 具有有可重配置的核级和向量级并行度的并行计算架构 [P] . 中国专利： CN112219209A . 2021-01-12
• 2. 内外连网络拓扑架构及自洽扩展该架构的并行计算系统 [P] . 中国专利： CN1921437B . 2010.05.12
• 3. Parallel computational architecture with reconfigurable core-level and vector-level parallelism [P] . GB2588719A . 2021-05-05

  机译： 并行计算架构具有可重新配置的核心级和矢量级并行性

• 4. PARALLEL COMPUTATIONAL ARCHITECTURE WITH RECONFIGURABLE CORE-LEVEL AND VECTOR-LEVEL PARALLELISM [P] . 美国专利： US2019385046A1 . 2019-12-19

  机译： 具有可重新配置的核心级别和矢量级别并行性的并行计算体系结构

• 5. PARALLEL COMPUTATIONAL ARCHITECTURE WITH RECONFIGURABLE CORE-LEVEL AND VECTOR-LEVEL PARALLELISM [P] . 世界知识产权组织专利： WO2019239254A1 . 2019-12-19

  机译： 具有可重新配置的核心级别和矢量级别并行性的并行计算体系结构

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• 5. High-Level Versus Low-Level Do-Loop Parallelization: Results for One Testcase of a Multi-Block Solver on a Shared Memory Parallel Vector Computer. [R] . Wijnandts, P., Vogels, M. E. S. 1997

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