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A HOMOMORPHIC PROCESSING UNIT (HPU) FOR ACCELERATING SECURE COMPUTATIONS UNDER HOMOMORPHIC ENCRYPTION
A HOMOMORPHIC PROCESSING UNIT (HPU) FOR ACCELERATING SECURE COMPUTATIONS UNDER HOMOMORPHIC ENCRYPTION
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机译：用于在同态加密下加速安全计算的同种形态处理单元（HPU）
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摘要
Fully homomorphic encryption integrated circuit (IC) chips, systems and associated methods are disclosed. In one embodiment, a method of operation for a number theoretic transform (NTT) butterfly circuit is disclosed. The (NTT) butterfly circuit includes a high input word path cross-coupled with a low word path. The high input word path includes a first adder/subtractor, and a first multiplier. The low input word path includes a second adder/subtractor, and a second multiplier. The method includes selectively bypassing the second adder/subtractor and the second multiplier, and reconfiguring the low and high input word paths into different logic processing units in response to different mode control signals.
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