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Processor having multiple cores, shared core extension logic, and shared core extension utilization instructions
Processor having multiple cores, shared core extension logic, and shared core extension utilization instructions
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机译：具有多个核心，共享核心扩展逻辑和共享核心扩展利用率指令的处理器
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摘要
An apparatus of an aspect includes a plurality of cores and shared core extension logic coupled with each of the plurality of cores. The shared core extension logic has shared data processing logic that is shared by each of the plurality of cores. Instruction execution logic, for each of the cores, in response to a shared core extension call instruction, is to call the shared core extension logic. The call is to have data processing performed by the shared data processing logic on behalf of a corresponding core. Other apparatus, methods, and systems are also disclosed.
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