首页>
外国专利>
FORWARD ERROR CORRECTION AND CYCLIC REDUNDANCY CHECK MECHANISMS FOR LATENCY-CRITICAL COHERENCY AND MEMORY INTERCONNECTS
FORWARD ERROR CORRECTION AND CYCLIC REDUNDANCY CHECK MECHANISMS FOR LATENCY-CRITICAL COHERENCY AND MEMORY INTERCONNECTS
展开▼
机译：延迟关键一致性和内存互连的前向纠错和循环冗余校验机制
展开▼
页面导航
摘要
著录项
相似文献
摘要
Systems, methods, and apparatuses can include transmission-side protocol stack circuitry comprising first cyclic redundancy check (CRC) circuitry to determine first CRC code for a first set of information and to determine second CRC code for a second set of information; and Flit encoding circuitry to encode a first portion of a Flit with the first set of information and the first CRC code, the Flit encoding circuitry to encode a second portion of the Flit with the second set of information and the second CRC code. Receiver-side protocol stack circuitry can include a low-latency path comprising first CRC check circuitry to perform a CRC check on a first portion of a received Flit. Receiver-side protocol stack circuitry can include a non-low-latency path comprising forward error correction (FEC) decoder circuitry to perform FEC on received Flits, and second CRC check circuitry to perform CRC check on received Flits that pass FEC.
展开▼
