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Arithmetic logic unit with normal and accelerated performance modes using differing numbers of computational circuits

机译：算术逻辑单元，具有使用不同数量的计算电路的正常和加速性能模式

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摘要

A processor includes a front end including circuitry to decode a first instruction to set a performance register for an execution unit and a second instruction, and an allocator including circuitry to assign the second instruction to the execution unit to execute the second instruction. The execution unit includes circuitry to select between a normal computation and an accelerated computation based on a mode field of the performance register, perform the selected computation, and select between a normal result associated with the normal computation and an accelerated result associated with the accelerated computation based on the mode field.

机译：处理器包括前端，包括用于解码用于执行执行单元的性能寄存器的第一指令的电路和第二指令的电路，以及包括将第二指令分配给执行单元以执行第二指令的电路以执行第二指令的分配器。执行单元包括基于性能寄存器的模式场进行正常计算和加速计算的电路，执行所选择的计算，并在与正常计算相关联的正常结果和与加速计算相关联的加速结果之间进行选择基于模式字段。

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公开/公告号US11010166B2

专利类型
公开/公告日2021-05-18

原文格式PDF
申请/专利权人 INTEL CORPORATION;
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申请/专利号US201615087854
发明设计人 DEBABRATA MOHAPATRA;PERRY H. WANG;XIANG ZOU;SANG KYUN KIM;DEEPAK A. MATHAIKUTTY;GAUTHAM N. CHINYA;
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申请日2016-03-31
分类号G06F9/302;G06F9/318;G06F9/30;
国家 US
入库时间 2022-08-24 18:43:20

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