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ARRAY OF THREE-GATE FLASH MEMORY CELLS WITH INDIVIDUAL MEMORY CELL READ, PROGRAM AND ERASE
ARRAY OF THREE-GATE FLASH MEMORY CELLS WITH INDIVIDUAL MEMORY CELL READ, PROGRAM AND ERASE
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机译：三门闪存单元数组，具有单个内存单元格读取，程序和擦除
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摘要
A memory device comprising a substrate of semiconductor material and a plurality of memory cells formed on the substrate and arranged in an array of rows and columns, and a method of erasing the same. Each of the memory cells has a spaced apart source and drain region of the substrate, a channel region of the substrate extending between the source region and the drain region, a floating gate, drain region disposed over and insulated from a first portion of the channel region adjacent the source region; a select gate disposed over and insulated from the second portion of the channel region adjacent to , and a program-erase gate disposed over and insulated from the source region. The program-erase gate lines, alone or in combination with select gate lines or source lines, are arranged in a column direction, allowing each memory cell to be programmed, read, and erased individually.
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