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NANOFABRICATION AND DESIGN TECHNIQUES FOR 3D ICS AND CONFIGURABLE ASICS
NANOFABRICATION AND DESIGN TECHNIQUES FOR 3D ICS AND CONFIGURABLE ASICS
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机译：3D IC和可配置的ASIC的纳米制造与设计技术
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摘要
Various embodiments of the present technology provide for the ultra-high density heterogenous integration, enabled by nano-precise pick-and-place assembly. For example, some embodiments provide for the integration of modular assembly techniques with the use of prefabricated blocks (PFBs). These PFBs can be created on one or more sources wafers. Then using pick-and-place technologies, the PFBs can be selectively arranged on a destination wafer thereby allowing Nanoscale- aligned 3D Stacked Integrated Circuit (N3-SI) and the Microscale Modular Assembled ASIC (M2A2) to be efficiently created. Some embodiments include systems and techniques for the construction of construct semiconductor devices which are arbitrarily larger than the standard photolithography field size of 26 x 33mm, using pick-and-place assembly.
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