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PROCEDURE AND PROCEDURES FOR THE EXECUTION OF A STABLE SPECIAL QUALIFICATION WITH A SHORT-TERM LATE

机译:执行稳定的特殊资格的程序和程序,短期迟到

摘要

Device and method for sorting with short latency. For example, a processor version has: an input switch to receive a set of N input values to be sorted in a sorting order; comparison circuits for parallel comparison of each input value with all other input values for producing at least N*(N-1)/2 comparative result values; Matrix production circuits and/or logic for generating a result matrix with a line associated with each input value, with several bits in each line having comparative result values showing the results of comparisons with other input values,where a first region of the result matrix is to store a first set of bits having N*(N-1)/2 comparative result values and a second region of the result matrix, compared to the first region, is to store a second set of bits having an inversion of N*(N-1)/2 comparative result values; a parallel addition switch to perform parallel bits additions in each line to produce N unambiguous result values; and sorting switches to indicate in the N clear result values to return the sorting order.
机译:用短延迟进行排序的设备和方法。例如,处理器版本具有:输入交换机以接收一组以排序顺序进行排序的N个输入值;与所有其他输入值的并行比较的比较电路,用于产生至少n *(n-1)/ 2比较结果值的所有其他输入值;矩阵生产电路和/或逻辑,用于生成具有与每个输入值相关联的线的结果矩阵,每条线中具有多个比特,其具有比较结果值,该比较结果值显示与其他输入值的比较结果,其中结果矩阵的第一区域是为了存储具有n *(n-1)/ 2比较结果值的第一组比特和结果矩阵的第二区域,与第一区域相比,用于存储具有n *的反转的第二组比特( N-1)/ 2比较结果值;并行加法开关以在每行中执行并行位添加以产生n明确的结果值;并排序切换以在N个清除结果中指示返回排序顺序。

著录项

  • 公开/公告号DE102020131852A1

    专利类型

  • 公开/公告日2021-09-23

    原文格式PDF

  • 申请/专利权人 INTEL CORPORATION;

    申请/专利号DE202010131852

  • 申请日2020-12-01

  • 分类号G06F7/02;G06F15/80;G06T1/20;

  • 国家 DE

  • 入库时间 2022-08-24 21:13:36

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