首页>
外国专利>
INSTRUCTION WITHERING-BASED MULTI-INSTRUCTION OUT-OF-ORDER TRANSMISSION METHOD AND PROCESSOR
INSTRUCTION WITHERING-BASED MULTI-INSTRUCTION OUT-OF-ORDER TRANSMISSION METHOD AND PROCESSOR
展开▼
机译：基于指令的基于指令的多指令无序传输方法和处理器
展开▼
页面导航
摘要
著录项
相似文献
摘要
An instruction withering-based multi-instruction out-of-order transmission method and a processor, belonging to the field of processor designs. A tedious arbitration structure in conventional transmission architecture is abandoned, and an instruction withering circuit is increased. An instruction age array is used to characterize the time for which the instruction is stored in the CPU. In addition, a wakeup state bit is added. An instruction which has exceeded a withering threshold is stored in a deposition pool for direct transmission by the CPU. Furthermore, circuit structures such as an instruction request circuit, an instruction allocation circuit and a wakeup circuit are improved, effectively improving the timing of a key path in a multi-instruction transmission processor. When waking up instructions, instructions having a short execution cycle are woken up by a delay, and instructions having a long execution cycle are pre-woken up, so as to ensure that the instructions can be executed in a back-to-back manner, thereby satisfying the requirements of a high performance to power consumption ratio, a low delay and a high IPC in a modern super scalar out-of-order processor, and solving the problems in the prior art that the number of table entries in a transmission queue of a processor is increasing and the delay is also increasing.
展开▼
