A high-speed data buffer for next-generation DDR6/7 LR-DIMM server platform applications is presented. The high-speed data buffer system for the next-generation DDR6/7 LR-DIMM server platform application proposed in the present invention receives a low-speed clock input from the CPU and receives the clock from the low-power clocking interface and the low-power clocking interface including an additional clock buffer for the high-speed clock. A plurality of DRAMs that receive input and convert to a high-speed clock through ILFM, and a plurality of data buffers that receive clocks from each DRAM and include a transmitter and a receiver, each of the plurality of data buffers increasing the data transmission bandwidth To achieve this, a multi-stage inductive differential amplifier is used for the data buffer.
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