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首页> 外文会议>12th International Workshop on Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2002, Sep 11-13, 2002, Seville, Spain >Minimizing Spurious Switching Activities in CMOS Circuits
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Minimizing Spurious Switching Activities in CMOS Circuits

机译：最小化CMOS电路中的杂散开关活动

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摘要

In combinatorial blocks of static CMOS circuits transistor sizing can be applied for delay balancing in order to guarantee synchronously arriving signal slopes at the input of logic gates. Since the delay of a logic gate depends directly on transistor sizes, the variation of channel-widths and-lengths (W and L) allows to equalize different path delays without influencing the total propagation delay of the circuit. Unfortunately not only the delay, but also the total capacitance and the short-circuit power consumption of a circuit depend on the transistor sizes. In order to take this fact into account, the method is formulated as a multiobjective optimization problem, where the path delay differences and the power consumption are the design objectives. To achieve optimal results, transistor lengths have to be increased, which results in both increased gate capacitances and area. Splitting the long transistors counteracts this negative influence and reduces the power dissipated. Moreover, the so called "Zero-Delay" paths can be avoided by introducing additional delays.
机译：在静态CMOS电路的组合模块中，可以将晶体管大小调整应用于延迟平衡，以确保在逻辑门的输入端同步到达信号斜率。由于逻辑门的延迟直接取决于晶体管的尺寸，因此通道宽度和长度（W和L）的变化可以均衡不同的路径延迟，而不会影响电路的总传播延迟。不幸的是，不仅延迟，而且电路的总电容和短路功耗也取决于晶体管的尺寸。为了考虑到这一事实，将该方法表述为多目标优化问题，其中路径延迟差异和功耗是设计目标。为了获得最佳结果，必须增加晶体管的长度，这会增加栅极电容和面积。分开长晶体管抵消了这种负面影响，并降低了功耗。此外，可以通过引入额外的延迟来避免所谓的“零延迟”路径。

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