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12th International Workshop on Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2002, Sep 11-13, 2002, Seville, Spain

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1.Power Consumption Estimation of a C Program for Data-Intensive Applications

机译：用于数据密集型应用程序的C程序的功耗估算
- 作者：Eric Senn;Nathalie Julien;Johann Laurent;Eric Martin
- 会议名称：《12th International Workshop on Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2002, Sep 11-13, 2002, Seville, Spain》 | 2002年
2.Reducing Energy Consumption via Low-Cost Value Prediction

机译：通过低成本预测降低能耗
- 作者：Toshinori Sato;Itsujiro Arita
- 会议名称：《12th International Workshop on Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2002, Sep 11-13, 2002, Seville, Spain》 | 2002年
3.Selective Clock-Gating for Low Power/Low Noise Synchronous Counters

机译：低功耗/低噪声同步计数器的选择性时钟门控
- 作者：Pilar Parra;Antonio Acosta;Manuel Valencia
- 会议名称：《12th International Workshop on Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2002, Sep 11-13, 2002, Seville, Spain》 | 2002年
4.Robust SAT-Based Search Algorithm for Leakage Power Reduction

机译：鲁棒的基于SAT的漏电降低搜索算法
- 作者：Fadi A. Aloul;Soha Hassoun;Karem A. Sakallah;David Blaauw
- 会议名称：《12th International Workshop on Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2002, Sep 11-13, 2002, Seville, Spain》 | 2002年
5.Trends in Ultralow-Voltage RAM Technology

机译：超低压RAM技术的趋势
- 作者：Kiyoo Itoh
- 会议名称：《12th International Workshop on Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2002, Sep 11-13, 2002, Seville, Spain》 | 2002年
6.Transistor Level Synthesis Dedicated to Fast I.P. Prototyping

机译：晶体管级综合专用于快速I.P.原型制作
- 作者：A. Landrault;L. Pellier;A. Richard;C. Jay;M. Robert;D. Auvergne
- 会议名称：《12th International Workshop on Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2002, Sep 11-13, 2002, Seville, Spain》 | 2002年
7.The First Quartz Electronic Watch

机译：第一枚石英电子表
- 作者：Christian Piguet
- 会议名称：《12th International Workshop on Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2002, Sep 11-13, 2002, Seville, Spain》 | 2002年
8.An Approach to Energy Consumption Modeling in RC Ladder Circuits

机译：RC阶梯电路中的能耗建模方法
- 作者：M. Alioto;G. Palumbo;M. Poli
- 会议名称：《12th International Workshop on Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2002, Sep 11-13, 2002, Seville, Spain》 | 2002年
9.Automated Design Methodology for CMOS Analog Circuit Blocks in Complex Systems

机译：复杂系统中CMOS模拟电路模块的自动设计方法
- 作者：Razvan Ionita;Andrei Vladimirescu;Paul Jespers
- 会议名称：《12th International Workshop on Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2002, Sep 11-13, 2002, Seville, Spain》 | 2002年
10.Exploiting Metal Layer Characteristics for Low-Power Routing

机译：利用金属层特性实现低功耗布线
- 作者：Armin Windschiegl;Paul Zuber;Walter Stechele
- 会议名称：《12th International Workshop on Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2002, Sep 11-13, 2002, Seville, Spain》 | 2002年
11.Energy-Efficient Design of the Reorder Buffer

机译：重新排序缓冲区的节能设计
- 作者：Dmitry Ponomarev;Gurhan Kucuk;Kanad Ghose
- 会议名称：《12th International Workshop on Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2002, Sep 11-13, 2002, Seville, Spain》 | 2002年
12.Instrumentation Set-up for Instruction Level Power Modeling

机译：指令级功率建模的仪器设置
- 作者：S. Nikolaidis;N. Kavvadias;P. Neofotistos;K. Kosmatopoulos;T. Laopoulos;L. Bisdounis
- 会议名称：《12th International Workshop on Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2002, Sep 11-13, 2002, Seville, Spain》 | 2002年
13.Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level

机译：在门级测量CMOS数字电路的开关活动
- 作者：C. Baena;J. Juan-Chico;M.J. Bellido;P. Ruiz de Clavijo;C.J. Jimenez;M. Valencia
- 会议名称：《12th International Workshop on Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2002, Sep 11-13, 2002, Seville, Spain》 | 2002年
14.MDSP: A High-Performance Low-Power DSP Architecture

机译：MDSP：高性能，低功耗DSP架构
- 作者：F. Pessolano;J. Kessels;A. Peeters
- 会议名称：《12th International Workshop on Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2002, Sep 11-13, 2002, Seville, Spain》 | 2002年
15.Low-Power Asynchronous A/D Conversion

机译：低功耗异步A / D转换
- 作者：Emmanuel Allier;Laurent Fesquet;Marc Renaudin;Gilles Sicard
- 会议名称：《12th International Workshop on Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2002, Sep 11-13, 2002, Seville, Spain》 | 2002年
16.Minimizing Spurious Switching Activities in CMOS Circuits

机译：最小化CMOS电路中的杂散开关活动
- 作者：Artur Wroblewski;Florian Auernhammer;Josef A. Nossek
- 会议名称：《12th International Workshop on Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2002, Sep 11-13, 2002, Seville, Spain》 | 2002年
17.Modeling Propagation Delay of MUX, XOR, and D-Latch Source-Coupled Logic Gates

机译：MUX，XOR和D锁存源耦合逻辑门的传播延迟建模
- 作者：M. Alioto;G. Palumbo
- 会议名称：《12th International Workshop on Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2002, Sep 11-13, 2002, Seville, Spain》 | 2002年
18.A Low Overhead Auto-Optimizing Bus Encoding Scheme for Low Power Data Transmission

机译：用于低功耗数据传输的低开销自动优化总线编码方案
- 作者：Claudia Kretzschmar;Robert Siegmund;Dietmar Mueller
- 会议名称：《12th International Workshop on Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2002, Sep 11-13, 2002, Seville, Spain》 | 2002年
19.A Technique to Generate CMOS VLSI Flip-Flops Based on Differential Latches

机译：基于差分锁存器的CMOS VLSI触发器生成技术
- 作者：Raul Jimenez;Pilar Parra;Pedro Sanmartin;Antonio Acosta
- 会议名称：《12th International Workshop on Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2002, Sep 11-13, 2002, Seville, Spain》 | 2002年
20.Output Waveform Evaluation of Basic Pass Transistor Structure

机译：基本通过晶体管结构的输出波形评估
- 作者：S. Nikolaidis;H. Pournara;A. Chatzigeorgiou
- 会议名称：《12th International Workshop on Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2002, Sep 11-13, 2002, Seville, Spain》 | 2002年
21.PA-ZSA (Power-A ware Zero-Slack Algorithm): A Graph-Based Timing Analysis for Ultra-Low Power CMOS VLSI

机译：PA-ZSA（Power-A ware零延迟算法）：超低功耗CMOS VLSI的基于图的时序分析
- 作者：Kyu-won Choi;Abhijit Chatterjee
- 会议名称：《12th International Workshop on Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2002, Sep 11-13, 2002, Seville, Spain》 | 2002年
22.Performance and Power Comparative Study of Discrete Wavelet Transform on Programmable Processors

机译：离散小波变换在可编程处理器上的性能和功耗比较研究
- 作者：N.D. Zervas;G. Pagkless;M. Dasigenis;D. Soudris
- 会议名称：《12th International Workshop on Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2002, Sep 11-13, 2002, Seville, Spain》 | 2002年
23.Resonant Multistage Charging of Dominant Capacitances

机译：主导电容的谐振多级充电
- 作者：Christoph Saas;Josef A. Nossek
- 会议名称：《12th International Workshop on Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2002, Sep 11-13, 2002, Seville, Spain》 | 2002年
24.Probabilistic Power Estimation for Digital Signal Processing Architectures

机译：数字信号处理架构的概率功率估计
- 作者：Achim Freimann
- 会议名称：《12th International Workshop on Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2002, Sep 11-13, 2002, Seville, Spain》 | 2002年
25.Register File Energy Reduction by Operand Data Reuse

机译：通过重用操作数来减少文件能量
- 作者：Hiroshi Takamura;Koji Inoue;Vasily G. Moshnyaga
- 会议名称：《12th International Workshop on Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2002, Sep 11-13, 2002, Seville, Spain》 | 2002年
26.Characterization of Normal Propagation Delay for Delay Degradation Model (DDM)

机译：时延退化模型（DDM）的正向传播时延表征
- 作者：Alejandro Millan;Jorge Juan;Manuel J. Bellido;Paulino Ruiz-de-Clavijo;David Guerrero
- 会议名称：《12th International Workshop on Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2002, Sep 11-13, 2002, Seville, Spain》 | 2002年
27.Clock Distribution Network Optimisation under Self-Heating and Timing Constraints

机译：自加热和定时约束下的时钟分配网络优化
- 作者：M.R. Casu;M. Graziano;G. Masera;G. Piccinini;M.M. Prono;M. Zamboni
- 会议名称：《12th International Workshop on Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2002, Sep 11-13, 2002, Seville, Spain》 | 2002年
28.An Improved Power Macro-Model for Arithmetic Datapath Components

机译：算术数据路径组件的改进的幂宏模型
- 作者：D. Helms;E. Schmidt;A. Schulz;A. Stammermann;W. Nebel
- 会议名称：《12th International Workshop on Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2002, Sep 11-13, 2002, Seville, Spain》 | 2002年
29.Dual Supply Voltage Scaling in a Conventional Power-Driven Logic Synthesis Environment

机译：常规电源驱动逻辑综合环境中的双电源电压缩放
- 作者：Torsten Mahnke;Walter Stechele;Wolfgang Hoeld
- 会议名称：《12th International Workshop on Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2002, Sep 11-13, 2002, Seville, Spain》 | 2002年
30.Crosstalk Measurement Technique for CMOS ICs

机译：CMOS IC的串扰测量技术
- 作者：F. Picot;P. Coll;D. Auvergne
- 会议名称：《12th International Workshop on Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2002, Sep 11-13, 2002, Seville, Spain》 | 2002年
31.Dynamic Voltage Scheduling for Real Time Asynchronous Systems

机译：实时异步系统的动态电压调度
- 作者：Mohammed Es Salhiene;Laurent Fesquet;Marc Renaudin
- 会议名称：《12th International Workshop on Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2002, Sep 11-13, 2002, Seville, Spain》 | 2002年
32.Designing Carry Look-Ahead Adders with an Adiabatic Logic Standard-Cell Library

机译：使用绝热逻辑标准单元库设计进位超前加法器
- 作者：Antonio Blotti;Maurizio Castellucci;Roberto Saletti
- 会议名称：《12th International Workshop on Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2002, Sep 11-13, 2002, Seville, Spain》 | 2002年
33.Design and Realization of a Low Power Register File Using Energy Model

机译：基于能量模型的低功耗寄存器文件的设计与实现
- 作者：Xue-mei Zhao;Yi-zheng Ye
- 会议名称：《12th International Workshop on Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2002, Sep 11-13, 2002, Seville, Spain》 | 2002年
34.Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level

机译：逻辑电平下CMOS数字电路的高效快速电流曲线估计
- 作者：Paulino Ruiz-de-Clavijo;Jorge Juan;Manuel J. Bellido;Alejandro Millan;David Guerrero
- 会议名称：《12th International Workshop on Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2002, Sep 11-13, 2002, Seville, Spain》 | 2002年
35.Low-Power FSMs in FPGA: Encoding Alternatives

机译：FPGA中的低功耗FSM：编码替代方案
- 作者：G. Sutler;E. Todorovich;S. Lopez-Buedo;E. Boemo
- 会议名称：《12th International Workshop on Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2002, Sep 11-13, 2002, Seville, Spain》 | 2002年
- low-power;
- finite state machine;
- FPGA;
- one-hot;
- state encoding;
36.Impact of Technology in Power-Grid-Induced Noise

机译：技术对电网感应噪声的影响
- 作者：Juan-Antonio Carballo;Sani R. Nassif
- 会议名称：《12th International Workshop on Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2002, Sep 11-13, 2002, Seville, Spain》 | 2002年
37.Modeling of Propagation Delay of a First Order Circuit with a Ramp Input

机译：具有斜坡输入的一阶电路的传播延迟建模
- 作者：Rosario Mita;Gaetano Palumbo
- 会议名称：《12th International Workshop on Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2002, Sep 11-13, 2002, Seville, Spain》 | 2002年
38.A New Methodology for Efficient Synchronization of RNS-Based VLSI Systems

机译：基于RNS的VLSI系统高效同步的新方法
- 作者：Daniel Gonzalez;Antonio Garcia;Graham A. Jullien;Javier Ramirez;Luis Parrilla;Antonio Lloris
- 会议名称：《12th International Workshop on Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2002, Sep 11-13, 2002, Seville, Spain》 | 2002年
39.A Low Energy Clustered Instruction Memory Hierarchy for Long Instruction Word Processors

机译：用于长指令字处理器的低能耗集群指令存储器层次结构
- 作者：Murali Jayapala;Francisco Barat;Pieter Op de Beeck;Francky Catthoor;Geert Deconinck;Henk Corporaal
- 会议名称：《12th International Workshop on Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2002, Sep 11-13, 2002, Seville, Spain》 | 2002年
40.A New Methodology to Design Low-Power Asynchronous Circuits

机译：设计低功耗异步电路的新方法
- 作者：Oscar Garnica;Juan Lanchares;Roman Hermida
- 会议名称：《12th International Workshop on Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2002, Sep 11-13, 2002, Seville, Spain》 | 2002年
41.Offline Data Profiling Techniques to Enhance Memory Compression in Embedded Systems

机译：离线数据分析技术可增强嵌入式系统中的内存压缩
- 作者：Luca Benini;Alberto Macii;Enrico Macii
- 会议名称：《12th International Workshop on Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2002, Sep 11-13, 2002, Seville, Spain》 | 2002年
42.A Compact Charge-Based Propagation Delay Model for Submicronic CMOS Buffers

机译：亚微米CMOS缓冲器的紧凑的基于电荷的传播延迟模型
- 作者：Jose Luis Rossello;Jaume Segura
- 会议名称：《12th International Workshop on Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2002, Sep 11-13, 2002, Seville, Spain》 | 2002年
43.Performance Comparison of VLSI Adders Using Logical Effort

机译：使用逻辑努力的VLSI加法器性能比较
- 作者：Hoang Q. Dao;Vojin G. Oklobdzija
- 会议名称：《12th International Workshop on Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2002, Sep 11-13, 2002, Seville, Spain》 | 2002年
44.Optimal Two-Level Delay ― Insensitive Implementation of Logic Functions

机译：最佳两级延迟-逻辑功能的不敏感实现
- 作者：Igor Lemberski;Mark Josephs
- 会议名称：《12th International Workshop on Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2002, Sep 11-13, 2002, Seville, Spain》 | 2002年
45.Operating Region Modelling and Timing Analysis of CMOS Gates Driving Transmission Lines

机译：CMOS栅极驱动传输线的工作区域建模和时序分析
- 作者：Gregorio Cappuccino;Giuseppe Cocorullo
- 会议名称：《12th International Workshop on Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2002, Sep 11-13, 2002, Seville, Spain》 | 2002年
46.Power Efficient Vector Quantization Design Using Pixel Truncation

机译：使用像素截断的高效矢量量化设计
- 作者：Kostas Masselos;Panagiotis Merakos;Costas E. Goutis
- 会议名称：《12th International Workshop on Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2002, Sep 11-13, 2002, Seville, Spain》 | 2002年
47.Structure Independent Representation of Output Transition Time for CMOS Library

机译：CMOS库输出过渡时间的结构独立表示
- 作者：P. Maurine;N. Azemard;D. Auvergne
- 会议名称：《12th International Workshop on Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2002, Sep 11-13, 2002, Seville, Spain》 | 2002年
48.Synthetic Generation of Events for Address-Event-Representation Communications

机译：地址-事件-表示通信的事件的综合生成
- 作者：Alejandro Linares-Barranco;Gabriel Jimenez;Anton Civit;Bernabe Linares-Barranco
- 会议名称：《12th International Workshop on Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2002, Sep 11-13, 2002, Seville, Spain》 | 2002年
49.Clocking and Clocked Storage Elements in Multi-GHz Environment

机译：多GHz环境中的时钟和时钟存储元件
- 作者：Vojin G. Oklobdzija
- 会议名称：《12th International Workshop on Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2002, Sep 11-13, 2002, Seville, Spain》 | 2002年