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首页> 外文会议>12th International Workshop on Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2002, Sep 11-13, 2002, Seville, Spain >Impact of Technology in Power-Grid-Induced Noise
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Impact of Technology in Power-Grid-Induced Noise

机译：技术对电网感应噪声的影响

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摘要

Due to technology scaling, the trend for integrated circuits is towards higher power dissipation, higher frequency and lower supply voltages. As a result, the power supply current delivered through the on-chip power grid is increasing dramatically, which is recognized in the International Technology Roadmap for Semiconductors as a difficult challenge. Early power grid design and the addition of decoupling capacitance have become crucially important to control power-grid-induced noise. We show analytical relationships and simulation results that highlight key relationships between noise and technology parameters. The results underline trends in noise based on current roadmap predictions and reinforce the importance of early planning of global power grids.
机译：由于技术的扩展，集成电路的趋势是朝着更高的功耗，更高的频率和更低的电源电压发展。结果，通过片上电网传送的电源电流急剧增加，这在《国际半导体技术路线图》中被认为是一项艰巨的挑战。早期的电网设计和去耦电容的添加对于控制电网引起的噪声至关重要。我们展示了分析关系和仿真结果，这些关系和仿真结果突出了噪声与技术参数之间的关键关系。结果强调了基于当前路线图预测的噪声趋势，并加强了全球电网早期计划的重要性。

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