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首页> 外文会议>12th International Workshop on Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2002, Sep 11-13, 2002, Seville, Spain >Output Waveform Evaluation of Basic Pass Transistor Structure
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Output Waveform Evaluation of Basic Pass Transistor Structure

机译：基本通过晶体管结构的输出波形评估

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摘要

Pass transistor logic is a promising alternative to conventional CMOS logic for low-power high-performance applications due to the decreased node capacitance and reduced transistor count it offers. However, the lack of supporting design automation tools has hindered the widespread application of pass transistors. In this paper, a simple and robust modeling technique for the timing analysis of the basic pass transistor structure is presented. The proposed methodology is based on the actual phenomena that govern the operation of the pass transistor and enables fast timing simulation of circuits that employ pass transistors as controlled switches without significant loss of accuracy, compared to SPICE simulation.
机译：对于低功率高性能应用，传输晶体管逻辑是传统CMOS逻辑的有希望的替代品，因为它减少了节点电容并减少了晶体管数量。然而，缺乏支持的设计自动化工具阻碍了传输晶体管的广泛应用。本文提出了一种简单而健壮的建模技术，用于基本的传输晶体管结构的时序分析。与SPICE仿真相比，所提出的方法基于控制传输晶体管工作的实际现象，并且能够对采用传输晶体管作为受控开关的电路进行快速时序仿真，而不会造成准确性的显着损失。

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