Probabilistic Power Estimation for Digital Signal Processing Architectures

机译：数字信号处理架构的概率功率估计

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摘要

A method for estimating the power on architecture-level is described. Originally based on simulations with data sequences, the method is extended by an simulation-free approach. The statistical properties required for the underlying Dual-Bit-Type model are propagated through the circuit. The necessary computation formulas are presented. For both approaches, the model accuracy for base modules as for signal processing applications is comparably low.

机译：描述了一种在体系结构级别上估计功耗的方法。最初基于具有数据序列的模拟，该方法通过无模拟方法扩展。基础双位类型模型所需的统计属性通过电路传播。给出了必要的计算公式。对于这两种方法，基本模块的模型精度与信号处理应用程序的模型精度相比均较低。

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《12th International Workshop on Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2002, Sep 11-13, 2002, Seville, Spain》|2002年|p.458-467|共10页
会议地点 Seville(ES);Seville(ES)
作者
Achim Freimann;
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作者单位

Universitat Hannover Institut fur Mikroelektronische Schaltungen und Systeme;

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会议组织
原文格式 PDF
正文语种 eng
中图分类无线电电子学、电信技术;
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Probabilistic Power Estimation for Digital Signal Processing Architectures

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