A Technique to Generate CMOS VLSI Flip-Flops Based on Differential Latches

机译：基于差分锁存器的CMOS VLSI触发器生成技术

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In this comunication, a new technique to generate flip-flops based on differential structures is presented. This technique is based on the modification of size in transistors of existing differential latches. The limitations of the differential structures to apply this technique are few, so the range of application is high. The main application field is in mixed-signal analog-digital circuits, due to the low switching noise generated by these flip-flops. In this parameter, the behavior is similar in both the proposed flip-flop and the original structure, and better than existing flip-flops.

机译：在该通信中，提出了一种基于差分结构生成触发器的新技术。该技术基于现有差分锁存器的晶体管尺寸的修改。应用该技术的差分结构的局限性很小，因此应用范围很高。由于这些触发器产生的低开关噪声，主要应用领域是在混合信号模拟数字电路中。在该参数下，建议的触发器和原始结构的行为都相似，并且比现有触发器要好。

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来源
《12th International Workshop on Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2002, Sep 11-13, 2002, Seville, Spain》|2002年|p.209-218|共10页
会议地点 Seville(ES);Seville(ES)
作者
Raul Jimenez; Pilar Parra; Pedro Sanmartin; Antonio Acosta;
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作者单位

Instituto de Microelectronica de Sevilla-CNM / Universidad de Sevilla Avda. Reina Mercedes s, 41012-Sevilla, SPAIN;

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原文格式 PDF
正文语种 eng
中图分类无线电电子学、电信技术;
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1. Design-for-Test Techniques for Opens in Undetected Branches in CMOS Latches and Flip-Flops [J] . Zenteno Ramirez A., Espinosa G., Champac V. IEEE transactions on very large scale integration (VLSI) systems . 2007,第5期

机译：CMOS锁存器和触发器中未检测到的分支中的开路的测试设计技术
2. CMOS sense amplifier-based flip-flop with two N-C/sup 2/MOS output latches [J] . Jin-Cheon Kim, Young-Chan Jang Electronics Letters . 2000,第6期

机译：具有两个N-C / sup 2 / MOS输出锁存器的基于CMOS读出放大器的触发器
3. 0.8 V CMOS adiabatic differential switch logic circuit using bootstrap technique for low-voltage low-power VLSI [J] . Zhang Y., Chen H.H., Kuo J.B. Electronics Letters . 2002,第24期

机译：采用自举技术的低压低功耗VLSI 0.8 V CMOS绝热差分开关逻辑电路
4. A Technique to Generate CMOS VLSI Flip-Flops Based on Differential Latches [C] . Raul Jimenez, Pilar Parra, Pedro Sanmartin, International Workshop on Power and Timing Modeling, Optimization, and Simulation . 2002

机译：一种基于差分锁存生成CMOS VLSI触发器的技术
5. Low voltage, low power CMOS analog circuit design techniques for mobile, portable VLSI applications. [D] . Hung, Chung-Chih. 1997

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A Technique to Generate CMOS VLSI Flip-Flops Based on Differential Latches

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