Crosstalk Measurement Technique for CMOS ICs

机译：CMOS IC的串扰测量技术

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Signal integrity is of primary concern for designs in submicron processes. Based on the characterization of an industrial driver library in terms of crosstalk-induced noise possibility, we present a specific test structure to measure crosstalk signal on interconnect lines. An original implementation is proposed for direct amplitude and pulse width measurement of the crosstalk-induced parasitic signal. A validation is given with an HSPICE simulation of the extracted layout of the structure implemented in a 0.25μm process.

机译：信号完整性是亚微米工艺中设计的主要考虑因素。基于工业驱动器库在串扰引起的噪声可能性方面的表征，我们提出了一种特定的测试结构来测量互连线上的串扰信号。提出了一种用于串扰引起的寄生信号的直接幅度和脉冲宽度测量的原始实现。通过HSPICE仿真对以0.25μm工艺实现的结构的提取布局进行了验证。

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来源
《12th International Workshop on Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2002, Sep 11-13, 2002, Seville, Spain》|2002年|p.65-70|共6页
会议地点 Seville(ES);Seville(ES)
作者
F. Picot; P. Coll; D. Auvergne;
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作者单位

ATMEL Rousset, Zone Industrielle, 13106 Rousset, France;

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会议组织
原文格式 PDF
正文语种 eng
中图分类无线电电子学、电信技术;
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Crosstalk Measurement Technique for CMOS ICs

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