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首页> 外文会议>12th International Workshop on Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2002, Sep 11-13, 2002, Seville, Spain >Low-Power FSMs in FPGA: Encoding Alternatives
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Low-Power FSMs in FPGA: Encoding Alternatives

机译：FPGA中的低功耗FSM：编码替代方案

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摘要

In this paper, the problem of state encoding of FPGA-based synchronous finite state machines (FSMs) for low-power is addressed. Four codification schemes have been studied: First, the usual binary encoding and the One-Hot approach suggested by the FPGA vendor; then, a code that minimizes the output logic; finally, the so-called Two-Hot code strategy. FSMs of the MCNC and PREP benchmark suites have been analyzed. Main results show that binary state encoding fit well with small machines (up to 8 states), meanwhile One-Hot is better for large FSMs (over 16 states). A power saving of up to the 57 % can be achieved selecting the appropriate encoding. An area-power correlation has been observed in spite of the circuit or encoding scheme. Thus, FSMs that make use of fewer resources are good candidates to consume less power.
机译：本文解决了基于FPGA的低功耗同步有限状态机（FSM）的状态编码问题。已经研究了四种编码方案：首先，FPGA供应商建议使用常规的二进制编码和One-Hot方法。然后，是使输出逻辑最小化的代码；最后，就是所谓的“两码”策略。已分析了MCNC和PREP基准套件的FSM。主要结果表明，二进制状态编码非常适合小型机器（最多8个状态），而One-Hot更好地适用于大型FSM（超过16个状态）。选择适当的编码可以节省多达57％的电源。尽管有电路或编码方案，也已经观察到面积-功率相关性。因此，使用较少资源的FSM是消耗较少功率的良好候选者。

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