• 主题
高级搜索  >
历史搜索 清空历史
首页> 外文会议>12th International Workshop on Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2002, Sep 11-13, 2002, Seville, Spain >Operating Region Modelling and Timing Analysis of CMOS Gates Driving Transmission Lines
【24h】

Operating Region Modelling and Timing Analysis of CMOS Gates Driving Transmission Lines

机译：CMOS栅极驱动传输线的工作区域建模和时序分析

获取原文
获取原文并翻译 | 示例
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

The switching behaviour and the operating region of a complementary metal-oxide-semiconductor (CMOS) gate driving a resistance-inductance-capacitance (RLC) transmission line is investigated in this paper. Closed form expressions for the time the transistors operate in the saturation and triode region respectively are proposed. Closed form expressions show predictions within 10% of HSPICE results for a wide range of line and buffer parameters, making them suitable to be applied to the problem of buffer sizing, repeater insertion, short circuit power estimation and generally whenever the accurate knowledge of the operation of CMOS buffers driving a transmission line is required. In the paper useful hints for choosing the most appropriate model for the triode region of the transistors of the inductive-line driver are also given.
机译：本文研究了驱动电阻-电感-电容（RLC）传输线的互补金属氧化物半导体（CMOS）栅极的开关行为和工作区域。提出了晶体管分别在饱和区和三极管区工作的时间的闭式表达式。闭合形式的表达式显示了对各种行和缓冲区参数的HSPICE结果的10％以内的预测，使其适合于缓冲区大小，中继器插入，短路功率估计等问题，并且通常在精确掌握操作知识的情况下使用需要驱动传输线的CMOS缓冲器。在本文中，还提供了一些有用的提示，可为感应线驱动器的晶体管的三极管区域选择最合适的模型。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号