首页> 外文会议>16th Asian Test Symposium >Test Generation for Transistor Shorts using Stuck-at Fault Simulator and Test Generator
【24h】

Test Generation for Transistor Shorts using Stuck-at Fault Simulator and Test Generator

机译:使用卡住的故障模拟器和测试生成器生成晶体管短路的测试

获取原文
获取原文并翻译 | 示例

摘要

Test generation methods for transistor shorts using logic test environment are proposed. The fault models used are strong shorts and weak shorts, introduced in our earlier work. Our methodology consists of fault simulation, test generation and test compaction using gate-level tools to detect transistor faults but without resorting to use of transistor-level tools.
机译:提出了利用逻辑测试环境对晶体管短路进行测试生成的方法。在我们早期的工作中介绍了使用的故障模型是强短路和弱短路。我们的方法包括故障模拟,测试生成和使用门级工具检测晶体管故障的测试压缩,但不求助于晶体管级工具。

著录项

  • 来源
    《16th Asian Test Symposium》|2007年|271-274|共4页
  • 会议地点 Beijing(CN);Beijing(CN)
  • 作者单位

    Yoshinobu Higami@Graduate School of Science and Engineering, Ehime University Dept. of Electrical and Computer Engineering, University of Wisconsin-Madison--Kewal K. Saluja@Graduate School of Science and Engineering, Ehime University Dept. of Electrical and Computer Engineering, University of Wisconsin-Madison--Hiroshi Takahashi@Graduate School of Science and Engineering, Ehime University Dept. of Electrical and Computer Engineering, University of Wisconsin-Madison--Shin-ya Kobayashi@Graduate School of Science and Engineering, Ehime University Dept. of Electrical and Computer Engineering, University of Wisconsin-Madison--Yuzo Takamatsu@Graduate School of Science and Engineering, Ehime University Dept. of Electrical and Computer Engineering, University of Wisconsin-Madison--;

  • 会议组织
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 调整、测试;
  • 关键词

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号