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首页> 外文会议>1st International Conference on Semiconductor Technology Vol.1, May 27-30, 2001, Shanghai, China >The Simulation and Analysis of the SVX Technique for High-Voltage Devices
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The Simulation and Analysis of the SVX Technique for High-Voltage Devices

机译：高压设备SVX技术的仿真与分析

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摘要

A new high-voltage technique called Smart Voltage extension (SVX) using a CMOS basis to extend the operating voltage without requiring any modification of the process steps is simulated and analyzed in this paper. The SVX technique is a cost effective solution in combing HV devices with LV analog and digital circuit. Firstly, the different breakdown mechanisms that can take place in a LV transistor when one of its terminals is pushed beyond the voltage limit set by the technology are discussed. Then the according required technological additions or modification performed in the HV devices and special layout rules adopted in the SVX technique are presented. Secondly, the applicability and reliability of the SVX technique are verified by the two-dimensional process simulator ATHENA and the device simulator, ATLAS. At last, the simulated values are compared with the measured ones, which shows that the SVX technique is applicable.
机译：本文模拟并分析了一种新的高压技术，即基于CMOS的智能电压扩展（SVX）技术，该电压可扩展工作电压而无需修改任何工艺步骤。 SVX技术是将HV设备与LV模拟和数字电路结​​合在一起的一种经济高效的解决方案。首先，讨论了当LV晶体管的一个端子被推到超过该技术设置的电压极限时，在LV晶体管中可能发生的不同击穿机制。然后介绍了在HV设备中执行的所需技术添加或修改，以及SVX技术中采用的特殊布局规则。其次，通过二维过程仿真器ATHENA和设备仿真器ATLAS验证了SVX技术的适用性和可靠性。最后，将仿真值与实测值进行比较，表明SVX技术是适用的。

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