首页> 外文会议>1st International Conference on Semiconductor Technology Vol.1, May 27-30, 2001, Shanghai, China >A Novel Substrate P-N Junction Isolation for RF Integrated Inductors on Silicon
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A Novel Substrate P-N Junction Isolation for RF Integrated Inductors on Silicon

机译:用于硅上RF集成电感器的新型衬底P-N结隔离

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摘要

We present a new method for reducing the substrate-rated losses of integrated spiral inductors that directly forming the P-N junction isolation in the Si substrate to block the eddy currents. The substrate P-N junction can be realized in standard silicon technologies without additional processing steps. The impacts of junction depth and pitch on the inductor quality factor (Q) are studied extensively. Measurements based equivalent circuit parameters are demonstrated and experimental results show that deep substrate P-N junction isolation achieves good improvement. At 2-3GHz,the addition of the deep junction increases the inductor quality factor up to 20%, and the quality factor is found to increase with rising depth and decreasing pitch of junction.
机译:我们提出了一种减少集成螺旋电感器的基板额定损耗的新方法,该方法直接在Si基板中形成P-N结隔离以阻止涡流。可以通过标准的硅技术实现衬底P-N结,而无需其他处理步骤。结深和节距对电感品质因数(Q)的影响已得到广泛研究。演示了基于等效电路参数的测量结果,实验结果表明,深层衬底的P-N结隔离度有很好的改善。在2-3GHz处,深结的添加使电感器的品质因数提高了20%,并且发现品质因数随深度的增加和结距的减小而增加。

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