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首页> 外文会议>2010 27th International Conference on Microelectronics Proceedings >Nanoscaling of MOSFETs and the implementation of Schottky barrier S/D contacts
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Nanoscaling of MOSFETs and the implementation of Schottky barrier S/D contacts

机译：MOSFET的纳米尺度化和肖特基势垒S / D触点的实现

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摘要

This paper provides an overview of metallic source/drain (MSD) Schottky-barrier (SB) MOSFET technology. This technology offers several benefits for scaling CMOS, i.e., extremely low S/D series resistance, sharp junctions from S/D to channel and low temperature processing. A successful implementation of this technology needs to overcome new obstacles such as Schottky barrier height (SBH) engineering and careful control of SALICIDE process. Device design factors such as S/D to gate underlap, Si film thickness and oxide thickness affect device performance owing to their effects on the SB width. Recently, we have invested a lot of efforts on Pt- and Ni-silicide MSD SB-MOSFETs and achieved some promising results. The present work, together with the work of other groups in this field, places silicide MSD SB-MOSFETs as a competitive candidate for future generations of CMOS technology.
机译：本文概述了金属源极/漏极（MSD）肖特基势垒（SB）MOSFET技术。该技术为缩放CMOS提供了许多好处，即极低的S / D串联电阻，从S / D到通道的清晰结和低温处理。该技术的成功实施需要克服新的障碍，例如肖特基势垒高度（SBH）工程以及对SALICIDE工艺的仔细控制。由于对SB宽度的影响，器件设计因素（例如，栅底重叠的S / D，Si膜厚度和氧化物厚度）会影响器件性能。最近，我们在Pt和Ni硅化物MSD SB-MOSFET上投入了大量精力，并取得了可喜的成果。目前的工作以及该领域其他小组的工作，使硅化物MSD SB-MOSFET成为了下一代CMOS技术的竞争者。

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