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首页> 外文会议>BMEI 2012;International Conference on Biomedical Engineering and Informatics >Hardware implementation of SHA-3 candidate based on BLAKE-32
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Hardware implementation of SHA-3 candidate based on BLAKE-32

机译：基于BLAKE-32的SHA-3候选软件的硬件实现

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摘要

Quality of hardware implementation is an important factor in selecting the NIST SHA-3 competition finalists. As a third-round candidate algorithm of SHA-3, BLAKE algorithm achieved excellent performance in software implementation. In order to adapt to the resource-limited and high-speed system, this paper carried out a [4G] hardware architecture based on BLAKE-32 algorithm. To complete the calculation, our architecture divides each round cycle into two cycles and each cycle executes 4G functions. Therefore, by adopting this architecture, the resources consuming can be reduced and a higher working frequency can be achieved. After validating the Verilog implementation of our architecture on a FPGA platform, the simulating results show that our [4G]-BLAKE structure has several advantages as a 26.8% area reducing, an up to 112 MHz acceleration in maximum working frequency and an up to 2048 Mbit/s enhancement in maximum throughput rate.
机译：硬件实施质量是选择NIST SHA-3竞赛决赛选手的重要因素。作为SHA-3的第三轮候选算法，BLAKE算法在软件实现上取得了优异的性能。为了适应资源有限的高速系统，本文基于BLAKE-32算法进行了[4G]硬件架构的设计。为了完成计算，我们的体系结构将每个回合周期分为两个周期，每个周期执行4G功能。因此，通过采用这种架构，可以减少资源消耗，并可以提高工作频率。在验证了我们在FPGA平台上的架构的Verilog实现之后，仿真结果表明，我们的[4G] -BLAKE结构具有以下优点：减小了26.8％的面积，最大工作频率高达112 MHz的加速度，以及高达2048最大吞吐速率提高了Mbit / s。

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