FPGA implementation of the m-ary modular exponentiation

机译：FPGA实现的三进制模块化幂运算

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Modular exponentiation is a key operation of RSA cryptosystem and is very time consuming for large operands. It is performed using successive modular multiplications. This paper describes hardware architecture of the m-ary modular exponentiation with reduced number of Montgomery modular multiplications. This architecture has been implemented on FPGA circuit of Virtex-2 and presents best performances in terms of computation time and occupied resources.

机译：模幂运算是RSA密码系统的关键操作，对于大型操作数而言非常耗时。它使用连续的模数乘法执行。本文介绍了数量减少的蒙哥马利模乘的m元模幂的硬件体系结构。该架构已在Virtex-2的FPGA电路上实现，并且在计算时间和占用资源方面均表现出最佳性能。

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来源
《2013 8th International Design and Test Symposium》|2013年|1-2|共2页
会议地点 Marrekesh(MA)
作者
Nadjia A.; Mohamed A.;
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作者单位

CDTA (Centre de Dev. des Technol. Av.), Algiers, Algeriac;

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会议组织
原文格式 PDF
正文语种 eng
中图分类
关键词
FPGA; Montgomery modular exponentiation; RSA;

机译：FPGA;蒙哥马利模块化指数; RSA;;

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3. Efficient PSoC Implementation of Modular Multiplication and Exponentiation Based on Serial-Parallel Combination [J] . Issad M., Boudraa B., Anane M., Journal of circuits, systems and computers . 2019,第13期

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4. FPGA implementation of the m-ary modular exponentiation [C] . Nadjia A., Mohamed A. IEEE Design and Test Symposium . 2013

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7. FPGA Implementation of Modular Exponentiation [O] . Alexander Tiountchik, Elena Trichina 2008

机译：模幂运算的FPGA实现

FPGA implementation of the m-ary modular exponentiation

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