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首页> 外文会议>2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip >Register allocation for high-level synthesis of hardware accelerators targeting FPGAs
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Register allocation for high-level synthesis of hardware accelerators targeting FPGAs

机译：寄存器分配，用于针对FPGA的硬件加速器的高级综合

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摘要

This work evaluates the benefits of several register allocation strategies as part of a design flow for automatic generation of application-specific hardware accelerators targeting FPGAs. As usage of vendor-specific design tools is mandatory for system designs targeting FPGAs, high-level synthesis has to account for the optimization capabilities already implemented in these design tools. In addition, FPGA-specific hardware characteristics have to be considered as well. Therefore, several register allocation strategies are evaluated in the context of a GCC based C to HDL design flow for application-specific hardware accelerators. Evaluation was done by means of several example designs from typical application domains for embedded systems. These designs were synthesized using the ISE design suite with either area or speed as an optimization criteria. Synthesis results for Spartan 6 and Artix 7 FPGAs show that with regards to clock frequency and area requirements, register allocation strategy should be kept simple when generating HDL code as an input for FPGA vendor-specific design tools.
机译：这项工作评估了几种寄存器分配策略的好处，这些策略是自动生成针对FPGA的专用硬件加速器的设计流程的一部分。由于针对FPGA的系统设计必须使用特定于供应商的设计工具，因此高级综合必须考虑这些设计工具中已实现的优化功能。另外，还必须考虑特定于FPGA的硬件特性。因此，在针对专用硬件加速器的基于GCC的C到HDL设计流程的上下文中，评估了几种寄存器分配策略。评估是通过嵌入式系统典型应用领域的几个示例设计完成的。这些设计是使用ISE设计套件以面积或速度作为优化标准进行综合的。 Spartan 6和Artix 7 FPGA的综合结果表明，关于时钟频率和面积要求，在生成HDL代码作为FPGA厂商特定设计工具的输入时，寄存器分配策略应保持简单。

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