The enhancement of MOSFET electric performance through strain engineering by refilled sige as Source and Drain

机译：通过重新填充信号作为源极和漏极，通过应变工程来增强MOSFET的电性能

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Mismatched lattice constants between SiGe and silicon can cause the strain making the mobility improved. SiGe are grown underneath the channel apparently to form global strain over the whole devices, while Source/Drain refilled with SiGe would squeeze or pull up the devices uni-axially. The ID-VG characteristics curves and the maximum trans-conductance (gm) using strain engineering are observed to be superior to the baseline. Nevertheless, the breakdown voltages with strain engineering no longer enjoy as robustly as ones without.

机译：SiGe和硅之间的晶格常数不匹配会导致应变，从而提高迁移率。 SiGe明显生长在通道下方，从而在整个器件上形成整体应变，而重新填充SiGe的源极/漏极将单轴挤压或拉高器件。观察到使用应变工程的I D -V G 特性曲线和最大跨导（g m ）优于基线。然而，采用应变工程的击穿电压不再像没有应变电压时那样具有强大的承受能力。

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来源
《2013 IEEE 5th International Nanoelectronics Conference.》|2013年|p.251-253|共3页
会议地点 Singapore(SG);Singapore(SG)
作者
Yang Hsin-Chia; Li Chao-Wang; Liao Wen-Shiang; Du Chong-Kuan; Wang Mu-Chun; Yang Jie-Min; Lian Chun-Wei; Liu Chuan-Hsi;
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作者单位

Dept. of Electronic Engineering, Minghsin University of Science Technology, Taiwan;

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会议组织
原文格式 PDF
正文语种 eng
中图分类微电子学、集成电路（IC）;微电子学、集成电路（IC）;
关键词
SiGe-Refilled Source/Drain; Strained Engineering;

机译：硅锗填充源/漏;应变工程;;

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专利

1. Strain engineering for electron mobility enhancement of strained Ge NMOSFET with SiGe alloy source/drain stressors [J] . Lee Chia-Feng, He Ren-Yu, Chen Kuan-Ting, Microelectronic Engineering . 2015,第apra期

机译：利用SiGe合金源/漏应力源提高应变Ge NMOSFET的电子迁移率的应变工程
2. A study on aggressive proximity of embedded SiGe with comprehensive source drain extension engineering for 32 nm node high-performance pMOSFET technology [J] . Hiroki Okamoto, Nobuaki Yasutake, Naoki Kusunoki, Solid-State Electronics . 2009,第7期

机译：利用全面的源极漏极扩展工程技术，针对32 nm节点高性能pMOSFET技术，积极探索嵌入式SiGe的接近性
3. Process optimizations to recessed e-SiGe source/drain for performance enhancement in 22 nm all-last high-k/metal-gate pMOSFETs [J] . Qin Changliang, Wang Guilei, Hong Peizhen, Solid-State Electronics . 2016,第SEPa期

机译：对凹入式e-SiGe源极/漏极进行工艺优化，以增强22 nm全高k /金属栅pMOSFET的性能
4. The enhancement of MOSFET electric performance through strain engineering by refilled sige as Source and Drain [C] . Yang Hsin-Chia, Li Chao-Wang, Liao Wen-Shiang, IEEE International Nanoelectronics Conference . 2013

机译：通过重新填充SiGe作为源极和排水管通过应变工程来增强MOSFET电性能
5. Source/drain engineering for extremely scaled MOSFETs. [D] . Zhang, Zhikuan. 2005

机译：适用于超大规模MOSFET的源/漏工程。
6. Strain engineering of transverse electric and transverse magnetic mode of material gain in GeSn/SiGeSn quantum wells [O] . Herbert S. Mączko, Robert Kudrawiec, Marta Gladysiewicz -1

机译：GeSn / SiGeSn量子阱中材料增益的横向和横向磁模式的应变工程
7. High Performance pMOSFETs with High Ge Fraction Strained SiGe-heterostructure-channel and Ultrashallow Source/Drain Formed by Selective B-Doped SiGe CVD [O] . Shinobu Takehiro, Masao Sakuraba, Junichi Murota, 2006

机译：具有高GE分数的高性能PMOSFET应变SiGE-异质结构 - 通过选择性B掺杂SiGE CVD形成的超肺源/漏极

The enhancement of MOSFET electric performance through strain engineering by refilled sige as Source and Drain

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