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Optimizing time-to-digital converter architecture for successive approximation time measurements

机译:优化时间数字转换器架构,以进行逐次逼近时间测量

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The paper is focused on the discussion of various variants of time-to-digital converter architectures for successive approximation time measurements (SA-TDC) realized strictly in the time domain. First, the revision of feedforward type architectures presented in previous works is carried out including propositions of optimized configurations that reduce the complexity of hardware blocks. Second, the feedback-based architecture for SA-TDCs is introduced where decisions in each conversion steps is taken by a single digital block. Furthermore, several versions of SA-TDC feedback-based architecture optimized in terms of compensation of logic propagation delays, removing redundancy of programmable delay lines and increasing energy efficiency are proposed.
机译:本文重点讨论了严格在时域中实现的逐次逼近时间测量(SA-TDC)的时间数字转换器架构的各种变体。首先,对先前工作中提出的前馈类型架构进行了修订,其中包括降低硬件模块复杂性的优化配置主张。其次,介绍了SA-TDC的基于反馈的体系结构,其中每个转换步骤中的决策由单个数字模块决定。此外,提出了几种版本的基于SA-TDC反馈的体系结构,这些版本在逻辑传播延迟的补偿,消除可编程延迟线的冗余以及提高能效方面进行了优化。

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