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首页> 外文会议>IEEE Nordic Mediterranean Workshop on Time-to-Digital Converters >Optimizing Time-to-Digital Converter Architecture for Successive Approximation Time Measurements
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Optimizing Time-to-Digital Converter Architecture for Successive Approximation Time Measurements

机译：用于连续近似时间测量的时间 - 数字转换器架构

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摘要

The paper is focused on the discussion of various variants of time-to-digital converter architectures for successive approximation time measurements (SA-TDC) realized strictly in the time domain. First, the revision of feedforward type architectures presented in previous works is carried out including propositions of optimized configurations that reduce the complexity of hardware blocks. Second, the feedback-based architecture for SA-TDCs is introduced where decisions in each conversion steps is taken by a single digital block. Furthermore, several versions of SA-TDC feedback-based architecture optimized in terms of compensation of logic propagation delays, removing redundancy of programmable delay lines and increasing energy efficiency are proposed.
机译：本文专注于讨论在时域中严格地实现的连续近似时间测量（SA-TDC）的各个数字转换器架构的各种变体。首先，执行先前作品中呈现的前馈类型架构的修订，包括降低硬件块复杂性的优化配置的命题。其次，介绍了SA-TDC的基于反馈的架构，其中每个转换步骤中的决策由单个数字块拍摄。此外，提出了在逻辑传播延迟补偿方面优化的若干版本的基于SA-TDC反馈的架构，除去可编程延迟线的冗余以及增加能效的冗余。

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