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首页> 外文会议>2013 International Conference on Circuits, Power and Computing Technologies >A low-power, area efficient design technique for wide fan-in domino logic based comparators
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A low-power, area efficient design technique for wide fan-in domino logic based comparators

机译：适用于基于扇形多米诺骨牌逻辑的比较器的低功耗，高效区域设计技术

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Domino CMOS logic circuits are widely used these days in the design of high-performance modules in modern day integrated chips and microprocessors. The feature of high speed and less area overhead of these logic circuits compared to other logic styles make them a popular choice in the design of high speed circuits. With advancements in high-speed processors, wide fan-in comparators are increasingly being employed in Arithmetic Logic Units (ALUs), Central Processing Units (CPUs). As the process technology and supply voltage are being scaled aggressively, the threshold voltage also has to be scaled down in a similar manner to achieve high performance. With this scaling of threshold voltage, the leakage power increases substantially at ultra deep sub-micron (UDSM) nodes. A circuit level technique has been proposed in this paper for domino logic based wide fan-in 32-bit comparators which incurs minimum area overhead while minimizing leakage & average power consumption with a slight delay penalty. Since, one cannot ignore the growing role of process variations at UDSM nodes, care has been taken to ensure that the overall circuit does not show wide difference in performance under supply voltage, process and temperature fluctuations. The proposed design shows a reduction in active leakage power of nearly 82% when compared to Adaptive Pseudo Dual Keeper (APDK) design and reduction of 66.67% when compared with APDK + leakage tolerant scheme. This design also reduces average power by 84% when compared with the APDK design and by 53.33% when pitted against the APDK + leakage tolerant scheme. Simulations have been carried out using the SILVACO EDA tool at nominal supply voltage of 0.9V, process technology of 32nm and operating frequency of 1.5 GHz.
机译：如今，Domino CMOS逻辑电路已广泛用于现代集成芯片和微处理器中高性能模块的设计中。与其他逻辑样式相比，这些逻辑电路具有高速和较少的区域开销的特点，使它们成为高速电路设计中的流行选择。随着高速处理器的进步，算术逻辑单元（ALU），中央处理单元（CPU）中越来越多地采用扇入比较器。随着制程技术和电源电压的不断提高，阈值电压也必须以类似的方式降低以实现高性能。通过阈值电压的这种缩放，在超深亚微米（UDSM）节点处的泄漏功率会大大增加。本文针对基于多米诺逻辑的宽扇入32位比较器提出了一种电路级技术，该技术可产生最小的面积开销，同时将泄漏和平均功耗降至最低，并具有轻微的延迟损失。由于不能忽视UDSM节点上工艺变化的日益增长的作用，因此已采取谨慎措施以确保整个电路在电源电压，工艺和温度波动下不会表现出很大的性能差异。与自适应伪双保持器（APDK）设计相比，拟议的设计显示有效泄漏功率降低了近82％，与APDK +耐泄漏方案相比，该设计方案降低了66.67％。与APDK设计相比，该设计还将平均功率降低了84％，与APDK +耐泄漏方案相比，平均功耗降低了53.33％。已经使用SILVACO EDA工具在0.9V的标称电源电压，32nm的工艺技术和1.5 GHz的工作频率下进行了仿真。

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