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首页> 外文会议>2014 9th International Microsystems, Packaging, Assembly and Circuits Technology Conference: Challenges of Change - Shaping the Future, 16th International Conference on Electronic Materials and packaging >Simulation 3D TSV for stress-strain characteristics under mechanical and thermo-mechanical loading
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Simulation 3D TSV for stress-strain characteristics under mechanical and thermo-mechanical loading

机译：模拟3D TSV在机械和热机械载荷下的应力应变特性

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This paper addresses the key stress and strain characteristics issues in three-dimensional integrated circuit (3D IC) packaging, which arise due to mechanical and thermo-mechanical loading. Although 3D IC packaging is known to suffer critical issues due to the reliance on non-mature technologies, it is valued for its high performance and miniaturization, achieved through the short vertical interconnections between individual chips and multi-chips that are stacked together. However, the reliability of through silicon via (TSV) and micro-bumps is still a significant concern and should thus be investigated further, due to the complexity of the architecture and microstructure. In this work, the 3D IC package used in the simulation model is built, after which the model is investigated under thermal cycle loading and mechanical bending cycle loading. In the analyses, both micro-bump and TSV are considered to exhibit bilinear isotropie hardening behaviors. The simulation results indicate that, under mechanical loading, the critical failure occurs on the outer micro-bump, while it is located on the outer TSV under thermo-mechanical loading. We thus posit that these fatigue failure sites could arise from the coefficient of thermal expansion (CTE) mismatch between the silicon chip and the TSV. Based on these findings, a simulation-based optimization methodology is developed with the aim of improving the overall 3D IC reliability. The main objective is to improve the TSV and micro-bump fatigue life when subjected to mechanical and thermo-mechanical loading by optimizing the design factors.
机译：本文解决了三维集成电路（3D IC）封装中的关键应力和应变特性问题，这些问题是由于机械和热机械载荷引起的。尽管由于对非成熟技术的依赖，众所周知3D IC封装会遇到严重问题，但3D IC封装由于其高性能和小型化而受到重视，这是通过单个芯片和堆叠在一起的多芯片之间的短垂直互连实现的。然而，由于架构和微结构的复杂性，贯穿硅通孔（TSV）和微凸块的可靠性仍是一个重要问题，因此应进一步研究。在这项工作中，建立了用于仿真模型的3D IC封装，然后在热循环载荷和机械弯曲循环载荷下研究了该模型。在分析中，微凸点和TSV都被认为具有双线性各向同性硬化行为。仿真结果表明，在机械载荷下，关键故障发生在外部微型凸点上，而在热机械载荷下，它位于外部TSV上。因此，我们认为这些疲劳失效部位可能是由硅芯片和TSV之间的热膨胀系数（CTE）不匹配引起的。基于这些发现，开发了一种基于仿真的优化方法，旨在提高整体3D IC的可靠性。主要目的是通过优化设计系数来延长在承受机械和热机械载荷时的TSV和微凸点疲劳寿命。

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