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首页> 外文会议>2014 Joint IEEE International Symposium on the Applications of Ferroelectrics, International Workshop on Acoustic Transduction Materials and Devices amp; Workshop on Piezoresponse Force Microscopy >Stress modeling for the impacts of flip chip process on the ultralow-k chips
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Stress modeling for the impacts of flip chip process on the ultralow-k chips

机译：针对倒装芯片工艺对超低k芯片影响的应力建模

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摘要

ULSI circuits are constantly improved by continuous scaling down the character sizes. Copper connections and the ultralow-k (ULK) materials as inter-layer dielectrics (ILD) and inter-metal dielectrics (IMD) were implemented. Therefore, the chip package interaction (CPI) becomes critical due to the mechanical properties deteriorate of ULK with high porosity. The reliability of ULK layer may be affected in flip chip process of the packaging. In this study, a three-dimensional finite element sub-modeling analysis was performed to investigate the stress distribution on Cu/ULK dielectric interconnect structures under flip chip reflow. The ULK layers and Cu connections on the surface of chip were homogenized to an equivalent thin layer, which makes contribution to the global stiffness. Considering the chip surface near the higher stress solder joint, the stresses in the sub-model including Cu/ULK dielectric interconnect structures was examined. The results show that the maximum stress occurs in vias and interfaces between TaN barrier layers and ultralow-k dielectric where the cracks most likely occur.
机译：ULSI电路通过不断缩小字符尺寸而不断得到改进。实现了铜连接以及作为层间电介质（ILD）和金属间电介质（IMD）的超低k（ULK）材料。因此，由于具有高孔隙率的ULK的机械性能下降，芯片封装相互作用（CPI）变得至关重要。在封装的倒装芯片工艺中，ULK层的可靠性可能会受到影响。在这项研究中，进行了三维有限元子建模分析，以研究倒装芯片回流下Cu / ULK介电互连结构上的应力分布。将芯片表面的ULK层和Cu连接均质化为等效的薄层，这有助于整体刚度。考虑到靠近较高应力焊点的芯片表面，检查了包括Cu / ULK介电互连结构的子模型中的应力。结果表明，最大应力出现在TaN势垒层与极可能发生裂纹的超低k电介质之间的通孔和界面中。

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