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首页> 外文会议>2015 International Conference on Communication Networks >Performance and analysis of 10T Full Adder using MTCMOS technique
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Performance and analysis of 10T Full Adder using MTCMOS technique

机译：使用MTCMOS技术的10T Full Adder的性能和分析

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Full Adder performs addition and therefore in microprocessor and digital signal processor, it is used for arithmetic operation, for comparison and for access the address in memory. Improvement of this circuit would impart a greater impact on the performance of large systems where it has been employed. For improvement of power and delay performance in full adder, the 10T structure based static energy recovery type full Adder (SERF) has been utilized with MTCMOS technique at 45nm technology. MTCMOS (Multi-Threshold Complementary Metal Oxide Semiconductor) technique has been emerged as a promising and popular circuit technique for further improvement in performance (i.e. reduction in delay and power minimization) of full adder. The paper here illustrates the analysis of leakage current, active power, delay and noise with power supply of (0.7 V). The reduction in power consumption in the structure represented is computed as 90.27nW and propagation delay of 10.24ns, which significantly improves and makes the circuit more efficient and reliable. The leakage current has been reduced and lies between 1.004¿¿¿1.771pA with different supply voltages from 0.5v to 0.9v. The adder has been analyzed for various parameters. All simulation results are performed with 45nm CMOS technology, 20ns access time and 0.05GHZ frequency using cadence virtuoso tool.
机译：Full Adder执行加法运算，因此在微处理器和数字信号处理器中，它用于算术运算，比较以及访问内存中的地址。对该电路的改进将对采用该电路的大型系统的性能产生更大的影响。为了提高全加器的功率和延迟性能，基于MT技术的45nm技术采用了基于10T结构的静态能量恢复型全加器（SERF）。 MTCMOS（多阈值互补金属氧化物半导体）技术已经成为一种有前途且流行的电路技术，用于进一步改善全加器的性能（即，减少延迟和最小化功率）。本文说明了在电源为（0.7 V）的情况下对泄漏电流，有功功率，延迟和噪声的分析。所表示结构的功耗降低计算为90.27nW，传播延迟为10.24ns，这大大改善了电路并使电路更高效，更可靠。泄漏电流已降低，并且在0.5v至0.9v的不同电源电压下位于1.004µ1.71.7pA之间。分析了加法器的各种参数。所有仿真结果均使用踏频虚拟工具，采用45nm CMOS技术，20ns访问时间和0.05GHZ频率执行。

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