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首页> 外文会议>2016 IEEE Annual India Conference >VLSI-design and FPGA-implementation of GMSK-demodulator architecture using CORDIC engine for low-power application
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VLSI-design and FPGA-implementation of GMSK-demodulator architecture using CORDIC engine for low-power application

机译：使用低功耗应用的CORDIC引擎的GMSK解调器架构的VLSI设计和FPGA实现

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摘要

This paper proposes low-power design of the Gaussian-Minimum Shift-Keying (GMSK) demodulator using baseband quadrature signals. High-level architecture of this demodulator incorporates CO-ordinate Rotation-DIgital Computer (CORDIC) engine to accept the in-phase and quadrature components from received GMSK signal to generate phase angle and magnitude of the GMSK signal vector at half the sampling frequency thereby reducing the power consumption. Additionally, the design of differentiator and synchronizer for the suggested GMSK demodulator has been carried out. The proposed demodulator is implemented in field-programmable gate-array (FPGA) and post-route simulated for functional verification. Thereafter, BER performance analysis of this design has been carried out in Additive White Gaussian Noise (AWGN) channel environment. Finally, the suggested architecture is synthesized and post-layout simulated using 90 nm CMOS technology node. It occupies a core area of 0.12 mm2 with 17770 gates and consumes 4.42 mW at 167 MHz of clock frequency.
机译：本文提出了使用基带正交信号的高斯最小移键控（GMSK）解调器的低功耗设计。该解调器的高级架构结合了坐标旋转数字计算机（CORDIC）引擎，以接收来自接收到的GMSK信号的同相和正交分量，从而以一半的采样频率生成GMSK信号矢量的相角和幅值，从而降低了功耗。此外，已经为建议的GMSK解调器设计了微分器和同步器。所提出的解调器在现场可编程门阵列（FPGA）中实现，并在路由后进行仿真以进行功能验证。此后，已经在加性高斯白噪声（AWGN）信道环境中进行了该设计的BER性能分析。最后，使用90 nm CMOS技术节点对建议的架构进行了综合和后布局仿真。它的核心面积为0.12 mm2，具有17770个门，在167 MHz的时钟频率下消耗4.42 mW。

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