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Transistor-level camouflaged logic locking method for monolithic 3D IC security

机译:用于单片3D IC安全的晶体管级伪装逻辑锁定方法

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摘要

This work proposes a novel method for transistor-level logic locking to address intellectual property (IP) piracy and reverse engineering attacks in monolithic three-dimensional (M3D) ICs. The proposed method locks logic gates by independently inserting parallel or serial locking transistors and camouflaged contacts in multiple tiers in M3D ICs. Without the correct key bits and confidential information for camouflaged contacts, the locked logic gates will malfunction and significantly alter power profiles, which makes reverse engineering attacks more difficult. The performance overhead of the proposed method is evaluated with ISCAS'85 benchmark circuits synthesized and placed with a customized M3D IC library. Case study on c6288 benchmark circuit shows that the proposed locking method with the correct key increases the power by only 0.26%. On average, this method consumes 2.3% more transistors than the baseline ISCAS'85 benchmark circuits.
机译:这项工作提出了一种用于晶体管级逻辑锁定的新颖方法,以解决单片三维(M3D)IC中的知识产权(IP)盗版和反向工程攻击。所提出的方法通过在M3D IC的多层中独立地插入并行或串行锁定晶体管和伪装触点来锁定逻辑门。如果没有正确的密钥位和伪装触点的机密信息,则锁定的逻辑门将无法正常工作,并且会严重改变功率分布,这使得逆向工程攻击更加困难。通过合成并放置有定制M3D IC库的ISCAS'85基准电路评估了所提出方法的性能开销。对c6288基准电路的案例研究表明,所提出的带有正确密钥的锁定方法仅能将功率提高0.26%。平均而言,此方法比ISCAS'85基准基准电路消耗的晶体管多2.3%。

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