Department of Computer Science and Engineering, Indian School of Mines, Dhanbad, India 826004;
Department of Computer Science and Engineering, Indian School of Mines, Dhanbad, India 826004;
Department of Computer Science and Engineering, Indian School of Mines, Dhanbad, India 826004;
Computer architecture; Hardware; Parallel algorithms; Field programmable gate arrays; Clocks; Signal generators; Gray-scale;
机译:用于自动生成形态图像过滤器FPGA中进化算法的混合实施
机译:用于硬件实现的演进型数字滤波器并行结构的设计和FPGA实现
机译:用于硬件实现的演进型数字滤波器并行结构的设计和FPGA实现
机译:基于FPGA的平行实现形态过滤器
机译:基于FPGA的位串行和位并行数字滤波器系统的功耗。
机译:高效实现FPGA对基于LMS自适应滤波器的FECG提取
机译:设计和FPGA高速并行冷杉过滤器的实现