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Design of low voltage flip-flop based on complementary pass-transistor adiabatic logic circuit

机译:基于互补通过晶体管绝热逻辑电路的低压触发器的设计

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This paper presents To design a low voltage flip-flops based on CPAL circuit. The Complementary Pass-Transistor Adiabatic Logic is used to release flip-flops circuits with DTCMOS (Dual Threshold CMOS) techniques. All circuits are simulated using 180nm Tanner model technology by varying supply voltages. Based on the simulation results, the flip-flop working along with the power-gating technique is realized by CPAL which work on low voltage medium which help to increase speed of the execution. We use Ac power supply which work as low power characteristics of complementary pass-transistor logic (CPL) circuit. Power-clock scheme is more suitable for the design of flip-flops using two phase sequential circuits because it helps to decrease more transistors. The Adiabatic flip-flop has large energy saving over wide range of frequencies.
机译:本文提出了一种基于CPAL电路的低压触发器的设计。互补的通过晶体管绝热逻辑用于通过DTCMOS(双阈值CMOS)技术释放触发器电路。所有电路均使用180nm Tanner模型技术通过改变电源电压进行仿真。基于仿真结果,CPAL实现了与电源门控技术一起工作的触发器,该控制器在低压介质上工作,有助于提高执行速度。我们使用交流电源,该电源用作互补的通过晶体管逻辑(CPL)电路的低功耗特性。功率时钟方案更适合使用两相顺序电路的触发器设计,因为它有助于减少更多的晶体管。绝热触发器可在很大的频率范围内节省大量能源。

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