Substrate influence on the behavior of capacitance hysteresis of III-V bilayered MOS stacks

机译：衬底对III-V双层MOS叠层电容迟滞行为的影响

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The dependence of ΔV_Hys on the stressing voltage for High-k Bi-layered InGaAs and InP substrate MOS capacitors is discussed in this work. Using different proportions of Al₂O₃ and HfO₂ dielectrics on a 10 nm thick gate insulator, the influence of each layer and its defects on the variations of the flat-band and hysteresis voltage is studied. Results show that increasing the thickness of the Al₂O₃ interfacial layer improves the quality of the structure in terms of reducing the hysteresis. InP stacks show the same tendencies of InGaAs stacks, but with a negligible impact of the stress in inversion on the hysteresis.

机译：在这项工作中，讨论了ΔV_{Hys 对高k双层InGaAs和InP衬底MOS电容器的应力电压的依赖性。在10 nm厚的栅极绝缘体上使用不同比例的Al _{2 O _{3 和HfO _{2 电介质，每一层的影响及其缺陷对研究了平带电压和磁滞电压的变化。结果表明，增加Al _{2 O _{3 界面层的厚度在降低磁滞方面提高了结构的质量。 InP叠层显示出与InGaAs叠层相同的趋势，但是反演应力对磁滞的影响可忽略不计。}}}}}}

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来源
《2017 32nd Symposium on Microelectronics Technology and Devices》|2017年|1-4|共4页
会议地点 Fortaleza(BR)
作者
Fernando L. Aguirre; Sebastián M. Pazos; Felix Palumbo; Igor Krylov; Moshe Eizenberg;
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作者单位

CONICET/GAIANN-CAC-CNEA, Nanoelectronics Laboratory, Electronics Engineering Dept. UTN.BA, Buenos Aires, Argentina CA;

CONICET/GAIANN-CAC-CNEA, Nanoelectronics Laboratory, Electronics Engineering Dept. UTN.BA, Buenos Aires, Argentina CA;

CONICET/GAIANN-CAC-CNEA, Nanoelectronics Laboratory, Electronics Engineering Dept. UTN.BA, Buenos Aires, Argentina CA;

Department of Materials Science and Engineering, Technion, Israel Institute of Technology, Haifa, Israel;

Department of Materials Science and Engineering, Technion, Israel Institute of Technology, Haifa, Israel;

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原文格式 PDF
正文语种 eng
中图分类
关键词
Hafnium compounds; Aluminum oxide; Hysteresis; Stress; Substrates; Capacitance; Capacitance-voltage characteristics;

机译：compounds化合物;氧化铝;磁滞;应力;基板;电容;电容电压特性;;

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Substrate influence on the behavior of capacitance hysteresis of III-V bilayered MOS stacks

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