Back gate influence on transistor efficiency of SOI nMOS Ω-gate nanowire down to 10nm width

机译：背栅对宽度小于10nm的SOI nMOSΩ栅纳米线的晶体管效率的影响

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This paper shows the influence of back gate bias on transistor efficiency of nMOS SOI Ω-gate nanowire, for different width and channel length. Threshold voltage and subthreshold swing present a higher variation with the back gate bias variation in wider devices. Long channel devices present better efficiency due to the better subthreshold swing, the same reason for the narrow devices have a better efficiency. Wider devices have a higher variation in efficiency when the back gate is biased. The transistor efficiency increases when the back gate is negative biased due to the better electrostatic coupling between gate and channel.

机译：本文显示了在不同宽度和沟道长度下，背栅偏压对nMOS SOIΩ栅纳米线的晶体管效率的影响。在较宽的器件中，阈值电压和亚阈值摆幅随背栅偏置变化而呈现出更高的变化。长通道设备由于具有更好的亚阈值摆幅而具有更高的效率，这与窄设备具有更高效率的原因相同。当背栅偏置时，较宽的器件在效率上的差异更大。当背栅为负偏置时，由于栅与沟道之间更好的静电耦合，晶体管效率会提高。

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来源
《2017 32nd Symposium on Microelectronics Technology and Devices》|2017年|1-4|共4页
会议地点 Fortaleza(BR)
作者
Vitor T. Itocazu; Luciano M. Almeida; Victor Sonnenberg; Paula G. D. Agopian; Sylvain Barraud; Maud Vinet; Olivier Faynot; Joao A. Martino;
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作者单位

LSI/PSI/USP, University of Sao Paulo, Sao Paulo, Brazil;

LSI/PSI/USP, University of Sao Paulo, Sao Paulo, Brazil;

LSI/PSI/USP, University of Sao Paulo, Sao Paulo, Brazil;

LSI/PSI/USP, University of Sao Paulo, Sao Paulo, Brazil;

CEA, LETI, Minatec Campus and University Grenoble Alpes, 38054 Grenoble, France;

CEA, LETI, Minatec Campus and University Grenoble Alpes, 38054 Grenoble, France;

CEA, LETI, Minatec Campus and University Grenoble Alpes, 38054 Grenoble, France;

LSI/PSI/USP, University of Sao Paulo, Sao Paulo, Brazil;

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原文格式 PDF
正文语种 eng
中图分类
关键词
Logic gates; Transistors; Integrated circuits; Silicon-on-insulator; MOS devices; Threshold voltage; Silicon;

机译：逻辑门;晶体管;集成电路;绝缘体上硅; MOS器件;阈值电压;硅;;

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3. Advanced 10nm Width Silicon-on-lnsulator Tri-Gate Transistors with NO Annealing of Gate Oxide Using Optimized Novel Silicon-on-lnsulator Realization Technology [J] . Sung Hwan Kim, Hyun Jun Bae, Chang Woo Oh, Japanese journal of applied physics . 2012,第4ISSUE2期

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4. Back gate influence on transistor efficiency of SOI nMOS Ω-gate nanowire down to 10nm width [C] . Vitor T. Itocazu, Luciano M. Almeida, Victor Sonnenberg, Symposium on Microelectronics Technology and Devices . 2017

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8. Gate oxide shorts in nMOS transistors: Electrical properties and lifetime prediction method [R] . Dababneh, S. A., Hawkins, C. F., Soden, J. M. 1994

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Back gate influence on transistor efficiency of SOI nMOS Ω-gate nanowire down to 10nm width

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