Experimental evaluation of mismatching on the analog characteristics of GC SOI MOSFETs

机译：GC SOI MOSFET的模拟特性不匹配的实验评估

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This paper presents an experimental study of mismatching on the analog characteristics of fully-depleted graded-channel SOI MOSFET in comparison to uniformly doped transistors. The study is carried out using dedicated structures to account for the mismatch that have been fabricated at the same chip and with the same technology. Important basic parameters such as threshold voltage and subthreshold slope were analyzed as well as analog parameters, namely transconductance, output conductance, Early voltage and intrinsic voltage gain.

机译：与均匀掺杂的晶体管相比，本文提出了对完全耗尽的渐变沟道SOI MOSFET的模拟特性不匹配的实验研究。该研究是使用专用结构来解决的，以解决在同一芯片上使用相同技术制造的不匹配问题。分析了重要的基本参数，例如阈值电压和亚阈值斜率，以及模拟参数，即跨导，输出电导，早期电压和固有电压增益。

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来源
《2017 32nd Symposium on Microelectronics Technology and Devices》|2017年|1-4|共4页
会议地点 Fortaleza(BR)
作者
Camila Restani Alves; Marcelo Antonio Pavanello; Michelly de Souza; Denis Flandre;
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作者单位

Department of Electrical Engineering, Centro Universitário FEI, São Bernardo do Campo, Brazil;

Department of Electrical Engineering, Centro Universitário FEI, São Bernardo do Campo, Brazil;

Department of Electrical Engineering, Centro Universitário FEI, São Bernardo do Campo, Brazil;

Department of Electrical Engineering, ICTEAM Institute, Université catholique de Louvain, Louvain-la-Neuve, Belgium;

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正文语种 eng
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关键词
Standards; MOSFET; Threshold voltage; Logic gates; Transconductance; Current measurement;

机译：标准; MOSFET;阈值电压;逻辑门;跨导;电流测量;;

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专利

1. Analog and radio-frequency (RF) performance evaluation of fully-depleted (FD) recessed-source/drain (Re-S/D) SOI MOSFETs [J] . Gopi Krishna Saramekala, Sarvesh Dubey, Pramod Kumar Tiwari Superlattices and microstructures . 2014,第deca期

机译：完全耗尽（FD）隐式源/漏（Re-S / D）SOI MOSFET的模拟和射频（RF）性能评估
2. Experimental Evaluation of Gate Architecture Influence on DG SOI MOSFETs Performance [J] . Julie Widiez, Jerome Lolivier, Maud Vinet, IEEE Transactions on Electron Devices . 2005,第8期

机译：栅极架构对DG SOI MOSFET性能影响的实验评估
3. A Strategy for Rapid Mismatch Evaluation of Transient Characteristics of CMOS Analog Cells [J] . RAFAEL LOPEZ-AHUMADA, RAFAEL RODRIGUEZ-MACIAS Analog Integrated Circuits and Signal Processing . 2003,第2期

机译：快速评估CMOS模拟单元瞬态特性的不匹配策略
4. Experimental evaluation of mismatching on the analog characteristics of GC SOI MOSFETs [C] . Camila Restani Alves, Marcelo Antonio Pavanello, Michelly de Souza, Symposium on Microelectronics Technology and Devices . 2017

机译：GC SOI MOSFET模拟特征不匹配的实验评价
5. Indium arsenide-on-SOI MOSFETs with extreme lattice mismatch. [D] . Wu, Bin. 2010

机译：SOI上的砷化铟MOSFET具有极高的晶格失配。
6. Study on the Thermal Conductivity Characteristics for Ultra-Thin Body FD SOI MOSFETs Based on Phonon Scattering Mechanisms [O] . Guohe Zhang, Junhua Lai, Yali Su, 2019

机译：基于声子散射机理的超薄体FD SOI MOSFET导热特性研究
7. Experimental evaluation of analog eigenmode transmission for short-range MIMO: array parameter independency and wideband characteristics [O] . Kentaro Murata, Naoki Honma, Masakuni Tsunezawa, 2015

机译：用于短距离MIMO的模拟特征模型传输的实验评价：阵列参数独立性和宽带特征
8. Theoretical-Experimental Analysis of the Effects of Grain Boundaries on the Electrical Properties of SOI (Silicon-on-Insulator) MOSFETS. [R] . Fossum, J. G. 1983

机译：晶界对sOI（绝缘体上硅）mOsFET电性能影响的理论实验分析。

Experimental evaluation of mismatching on the analog characteristics of GC SOI MOSFETs

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