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机译:完全耗尽(FD)隐式源/漏(Re-S / D)SOI MOSFET的模拟和射频(RF)性能评估
Department of Electronics and Communication Engineering, National Institute of Technology, Rourkela 769008, India;
Faculty of Electronics and Communication Engineering, Sriramswaroop Memorial University, Barabanki Road, Lucknow 22003, UP, India;
Department of Electronics and Communication Engineering, National Institute of Technology, Rourkela 769008, India;
Ultrathin-body (UTB); Fully-depleted (FD) systems-on-a-chip (SOC); Short-channel effects (SCEs); Figures-of-merit (FoM);
机译:短沟道全耗尽型凹陷源极/漏极(Re-S / D)UTB SOI MOSFET的阈值电压模型,包括衬底引起的表面电势效应
机译:三金属栅极(TMG)全耗尽型隐式源极/漏极(Re-S / D)SOI MOSFET中表面电势的二维分析模型
机译:具有高介电常数的短沟道全耗尽型凹陷源极/漏极(Re-S / D)SOI MOSFET的阈值电压模型
机译:基于ATLAS™的双金属栅(DMG)全耗尽(FD)隐式源/漏(Re-S / D)SOI MOSFET电气特性的仿真研究
机译:用于亚22纳米节点数字CMOS逻辑技术的基于锗的量子阱沟道MOSFET的工艺集成和性能评估
机译:FinFET和带铁电电容器的全耗尽绝缘体上硅(FDSOI)MOSFET的磁滞窗口研究
机译:完全耗尽的源极/漏极UTB SOI MOSFET亚阈值特性的建模和仿真,包括衬底引起的表面电势效应