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首页> 外文会议>2017 IEEE Nordic Circuits and Systems Conference: NORCHIP and International Symposium of System-on-Chip >Mitigating single-event upsets in COTS SDRAM using an EDAC SDRAM controller
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Mitigating single-event upsets in COTS SDRAM using an EDAC SDRAM controller

机译：使用EDAC SDRAM控制器缓解COTS SDRAM中的单事件干扰

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摘要

From deep space missions to low-earth orbit satellites, the natural radiation of space proves to be a hostile environment for electronics. Memory elements in particular are highly susceptible to radiation charge that if latched can cause single-event upsets (SEU, bit-flips) which lead to data corruption and even mission critical failures. On Earth, SDRAM devices are widely used as a cost-effective, high performance storage elements in almost every computer system. However, their physical design makes them highly susceptible to SEUs. Thus, their usage in space application is limited and usually avoided, requiring the use of radiation hardened components which are generally a few generations older and often much more expensive than COTS. In this paper, an off-chip SEU/MBU mitigation mechanism is presented that aims to drastically reduce the probability of data corruption inside a commercial-off-the-shelf (COTS) synchronous dynamic random access memory (SDRAM) using a triple modular redundant (TMR) scheme for data and periodic scrubbing. The proposed mitigation technique is implemented in a novel controller that will be used by the single-event upset detector (SEUD) experiment aboard the KTH MInature STudent (MIST) satellite project.
机译：从深空飞行任务到低地球轨道卫星，太空的自然辐射被证明是电子设备的不利环境。特别是存储元件非常容易受到辐射电荷的影响，如果将其锁定，则会导致单事件翻转（SEU，位翻转），从而导致数据损坏甚至关键任务失败。在地球上，SDRAM设备被广泛用作几乎每个计算机系统中的经济高效的高性能存储元件。但是，它们的物理设计使其非常容易受到SEU的影响。因此，它们在空间应用中的使用受到限制并且通常被避免，这要求使用辐射硬化组件，该辐射硬化组件通常比COTS老了几代，而且往往比COTS贵得多。在本文中，提出了一种片外SEU / MBU缓解机制，旨在通过使用三重模块化冗余大大降低商用现货（COTS）同步动态随机存取存储器（SDRAM）内部数据损坏的可能性。 （TMR）方案进行数据和定期清理。拟议的缓解技术是在新型控制器中实现的，该控制器将由KTH Matureature Student（MIST）卫星项目上的单事件翻转检测器（SEUD）实验使用。

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