The design of a FPGA⁃based the SDRAM controller for high⁃resolution video image processing is introduced in this paper. The SDRAM operating state is set to make it works in burst mode. SDRAM is controlled The video data is accessed by using the multi⁃line continuous SDRAM memory space under the control of the video time⁃sequence signals. The real⁃time storing and reading of video data are achieved under the control of pixel clock by increasing FIFO in the interface of video data to cache one line video. By changing the relevant parameters,all resolution video stream in the standard of VESA can be opera⁃ted. It has the characteristics of versatility,low system complexity,high reliability and scalability. The image reversion function was achieved and the practicality of the controller was verified in a particular model of airborne large⁃screen display system by SDRAM controller.% 本文介绍了一种基于FPGA的用于高分辨率视频图像处理的SDRAM控制器的设计方法。通过设置SDRAM的工作状态，使其工作在猝发模式。在视频时序信号控制下，用多行连续的SDRAM存储空间，存取视频数据。并在数据接口部分增加FIFO，缓存一行视频，在像素时钟控制下，实现视频数据实时的存储和读取。通过改变相关参数，能对所有VESA分辨率视频流进行操作。具有通用性强、系统复杂度低、可靠性高、可扩展等特点。在某型号的机载大屏显示器系统中，用该SDRAM控制器实现了图像的翻转等功能，也验证了该控制器的实用性。
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