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首页> 外文会议>2017 International Conference on Electrical, Electronics, Communication, Computer, and Optimization Techniques >Analysis of low power 7T SRAM cell employing improved SVL (ISVL) technique
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Analysis of low power 7T SRAM cell employing improved SVL (ISVL) technique

机译：利用改进的SVL（ISVL）技术分析低功耗7T SRAM单元

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With the increase in demand for low power memory, this is achieved by reducing the leakage currents. Power dissipation mainly occurs due to leakage currents of different forms such as Sub threshold & Gate leakage etc. and need to reduce these currents. This work mainly aims at design of low power 7T SRAM Cell by employing Improved Self Controllable Voltage Level (I-SVL) circuits. Simulation results show that there is enormous leakage current reduction in Improved Self Voltage Level method than Upper Lower-SVL 7T (UL-SVL) & Basic 7T SRAM Cell. I-SVL method resulted in 60% reduction of leakage current compared with UL-SVL SRAM 7T Cell and 68% reduction in comparison with Basic 7T SRAM cell. The entire Simulation is carried on 180nm CMOS technology, in Virtuoso platform of Cadence tool with a supply voltage of 0.7V.
机译：随着对低功率存储器的需求的增加，这通过减小泄漏电流来实现。功耗的产生主要是由于子阈值和栅极泄漏等不同形式的泄漏电流所致，需要降低这些电流。这项工作主要针对通过采用改进的自控电压电平（I-SVL）电路设计低功耗7T SRAM单元。仿真结果表明，与上下部SVL 7T（UL-SVL）和基本7T SRAM单元相比，改进的自电压电平方法可大大降低漏电流。与UL-SVL SRAM 7T单元相比，I-SVL方法使泄漏电流降低了60％，与Basic 7T SRAM单元相比，降低了68％。整个仿真在Cadence工具的Virtuoso平台上以180nm CMOS技术进行，电源电压为0.7V。

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